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PDF HC4046 Data sheet ( Hoja de datos )
| Número de pieza | HC4046 | |
| Descripción | Phase-Locked Loop | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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SL74HC4046
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC4046 phase-locked loop contains three phase
comparators, a voltage-controlled oscillator (VCO) and unity gain op-
amp DEMOUT. The comparators have two common signal inputs,
COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self-bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator 1
(an exclusive OR gate) provides a digital error signal PC1OUT and
maintains 90 degrees phase shift at the center frequency between SIGIN
and COMPIN signals (both at 50% duty cycle). Phase comparator 2
ORDERING INFORMATION
(with leading-edge sensing logic) provides digital error signals PC2OUT
SL74HC4046N Plastic
and PCPOUT and maintains a 0 degree phase shift between SIGIN and
SL74HC4046D SOIC
COMPIN signals (duty cycle is immaterial). The linear VCO produces an TA = -55° to 125° C for all packages
output signal VCOOUT whose frequency is determined by the voltage of
input VCOIN signal and the capacitor and resistors connected to pins
C1A, C1B, R1 and R2. The unity gain op-amp output DEMOUT with an external resistor is used where the VCOIN
signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps
to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,
frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency
conversion and motor speed control.
• Low Power Consumption Characteristic of CMOS Device
• Operating Speeds Similary to LS/ALSTTL
PIN ASSIGNMENT
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA Maximum (except SIGIN
COMPIN)
• Low Quiescent Current: 80 µA Maximum (VCO disabled)
and
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
PC3OUT
VCC
Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) VSS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
SLS
System Logic
Semiconductor
1 page  
SL74HC4046
(continued)
SLS
System Logic
Semiconductor
5 Page 
SL74HC4046
Figure 10. Offset Voltage at Demodulator Output as a
Function of VCOIN and RS
Figure 11A. Frequency Stability versus Ambient
Temperature: VCC = 3.0 V
Figure 11B. Frequency Stability versus Ambient
Temperature: VCC = 4.5 V
Figure 11C. Frequency Stability versus Ambient
Temperature: VCC = 6.0 V
Figure 12A. VCO Frequency (fVCO) as a Function of
the VCO Input Voltage (VVCOIN)
Figure 12B. VCO Frequency (fVCO) as a Function of
the VCO Input Voltage (VVCOIN)
490
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HC4046.PDF ] | |
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