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HC-5502B1 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HC-5502B1
Beschreibung SLIC Subscriber Line Interface Circuit
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 12 Seiten
HC-5502B1 Datasheet, Funktion
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HC-5502B1
April 1999 File Number 4127.2
SLIC Subscriber Line Interface Circuit
Features
[ /Title
(HC-
5502B
1)
/Sub-
ject
(SLIC
Sub-
scriber
Line
Inter-
face
Cir-
cuit)
/Autho
r ()
/Key-
words
(Inter-
sil
Semi-
con-
ductor,
RSLIC
18,
Tele-
com,
SLICs,
SLACs
, Tele-
phone,
Tele-
phony,
WLL,
Wire-
less
Local
Loop,
PBX,
Pri-
vate
Branch
Exchan
ge,
The Intersil SLIC incorporates many of the BORSHT
function on a single IC chip. This includes DC battery feed, a
ring relay driver, supervisory and hybrid functions. This
device is designed to maintain transmission performance in
the presence of externally induced longitudinal currents.
Using the unique Intersil dielectric isolation process, the
SLIC can operate directly with a wide range of station
battery voltages.
The SLIC also provides selective denial of power. If the PBX
system becomes overloaded during an emergency, the SLIC
will provide system protection by denying power to selected
subscriber loops.
The Intersil SLIC is ideally suited for the design of new digital
PBX systems, by eliminating bulky hybrid transformers.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
HC3-5502B1-5
HC4P5502B1-5
HC9P5502B1-5
0 to 75
0 to 75
0 to 75
24 Ld PDIP
28 Ld PLCC
24 Ld SOIC
PKG.
NO.
E24.6
N28.45
M24.3
Pinouts
HC-5502B1 (PDIP, SOIC)
TOP VIEW
TIP 1
RING 2
VB+ 3
C1 (NOTE) 4
C3 5
DG 6
RS 7
RD 8
TF 9
RF 10
VB- 11
BG 12
24 TX
23 AG
22 C4
21 RX
20 +IN
19 -IN
18 OUT
17 C2
16 RC
15 PD
14 GKD
13 SHD
NOTE: Optional.
• Low Cost Version of HC-5502B
• Capable of 12V or 5V (VB+) Operation
• Monolithic Integrated Device
• DI High Voltage Process
• Compatible With Worldwide PBX Performance
Requirements
• Controlled Supply of Battery Feed Current for Short Loops
(30mA)
• Internal Ring Relay Driver
• Low Power Consumption During Standby
• Switch Hook, Ground Key and Ring Trip Detection
Functions
• Selective Denial of Power to Subscriber Loops
Applications
• Solid State Line Interface Circuit for Analog and Digital PBX
Systems
• Direct Inward Dial (DID) Trunks
• Voice Messaging PBXs
• Related Literature
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
HC-5502B1 (PLCC)
TOP VIEW
4 3 2 1 28 27 26
C1 (NOTE) 5
C3 6
DG 7
N/C 8
RS 9
RD 10
TF 11
25 RX
24 +IN
23 -IN
22 N/C
21 OUT
20 C2
19 RC
12 13 14 15 16 17 18
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-724-7143| Copyright © Intersil Corporation 1999






HC-5502B1 Datasheet, Funktion
HC-5502B1
Pin Descriptions (Continued)
28 PIN
PLCC
24 PIN
DIP/SOIC SYMBOL
DESCRIPTION
26 22 C4 Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This ca-
pacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal
currents are induced onto the subscriber loop from nearby power lines and other noise sources. This ca-
pacitor is also required for the proper operation of ring trip detection. Typical value is 0.5µF to 1.0µF, 20V.
This capacitor should be nonpolarized.
27 23 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX)
and receive input (RX) terminals.
28 24 TX Transmit Output, Four Wire Side - A low impedance analog output which represents the differential volt-
age across Tip and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit’s spare
op amp) beyond this output to completely implement two to four wire conversion. This output is unbal-
anced and referenced to analog ground. Since the DC level of this output varies with loop current, capac-
itive coupling to the next stage is essential.
1, 8, 5, 22
NC No Internal Connection.
NOTE:
5. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
Functional Diagram
RING
VOLTAGE
RING SYNC
RING COMMAND
RS
RC
RD
TIP
RING
RELAY
150
TIP
150
2-WIRE
LOOP
VB-
RING
SECONDARY
PROTECTION
TF
VB-
BG
RF
150
RING
150
POWER DENIAL
PD
RING
CONTROL
RING
TRIP
LOOP
MONITORING
DIFF
AMP
+
SHD SWITCH HOOK
DETECTION
GKD GROUND KEY
DETECTION
TX TRANSMIT
OUTPUT
BATTERY
FEED
LOOP
CURRENT
LIMITER
+1
LINE
DRIVERS
-1
SLIC MICROCIRCUIT
+
OP
AMP
OUT
+IN
-IN
RX RECEIVE
INPUT
4-6

6 Page









HC-5502B1 pdf, datenblatt
HC-5502B1
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0926 0.1043 2.35
2.65
-
A1
0.0040 0.0118 0.10
0.30
-
B
0.013 0.020 0.33
0.51
9
C
0.0091 0.0125 0.23
0.32
-
D 0.5985 0.6141 15.20 15.60
3
E
0.2914 0.2992 7.40
7.60
4
e 0.05 BSC
1.27 BSC
-
H 0.394 0.419 10.00 10.65
-
h
0.010 0.029 0.25
0.75
5
L
0.016 0.050 0.40
1.27
6
N 24
24 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
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