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PDF NT5CB128M16BP Data sheet ( Hoja de datos )
| Número de pieza | NT5CB128M16BP | |
| Descripción | 2Gb DDR3 SDRAM B-Die | |
| Fabricantes | Nanya | |
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2Gb DDR3 SDRAM B-Die
NT5CB512M4BN / NT5CB256M8BN / NT5CB128M16BP
NT5CC512M4BN / NT5CC256M8BN / NT5CC128M16BP
Feature
1.5V ± 0.075V / 1.35V -0.0675V/+0.1V (JEDEC
Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK, )
Programmable Latency: 6, 7, 8, 9, 10, 11
Programmable Additive Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8 bit prefetch architecture
Output Driver Impedance Control
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS compliance and Halogen free
Packages:
78-Ball BGA for x4 & x8 components
96-Ball BGA for x16 components
Description
The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing
2,147,483,648 bits. It is internally configured as an octal-bank DRAM.
The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank, 32Mbit x 8 I/O x 8 bank or 16Mbit x 16 I/O x 8 bank device. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks
(CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ± 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA
packages.
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08 / 2010
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2Gb DDR3 SDRAM B-Die
NT5CB512M4BN / NT5CB256M8BN / NT5CB128M16BP
NT5CC512M4BN / NT5CC256M8BN / NT5CC128M16BP
Input / Output Functional Description
Symbol
Type
Function
CK,
Input
Clock: CK and are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of .
CKE
, ,
DM, (DMU, DML)
BA0 - BA2
A0 – A14
A12 /
DQ
DQL,
DQU,
DQS,(),
DQSL,(),
DQSU,(),
Input
Input
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh
operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit.
After VREF has become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain
to this input. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
Chip Select: All commands are masked when is registered high. provides for external rank
selection on systems with multiple memory ranks. is considered part of the command code.
Command Inputs: , and (along with ) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
Input
sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges
of DQS. For x8 device, the function of DM or TDQS / is enabled by Mode Register A11 setting
in MR1
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Input
Precharge command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs: Provide the row address for Activate commands and the column address for
Input
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/ have additional function as below. The address inputs also provide the op-code
during Mode Register Set commands.
Input
Burst Chop: A12/ is sampled during Read and Write commands to determine if burst chop (on
the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
Input/output Data Inputs/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered
with write data. The data strobes DQS, DQSL, DQSU are paired with differential signals , ,
Input/output
, respectively, to provide differential pair signaling to the system during both reads and writes.
DDR3 SDRAM supports differential data strobe only and does not support single-ended.
REV 1.1
08 / 2010
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5 Page 
2Gb DDR3 SDRAM B-Die
NT5CB512M4BN / NT5CB256M8BN / NT5CB128M16BP
NT5CC512M4BN / NT5CC256M8BN / NT5CC128M16BP
4. The DDR3 DRAM will keep its on-die termination in high impedance state as long as is asserted. Further, the
DRAM keeps its on-die termination in high impedance state after de-assertion until CKE is registered HIGH. The
ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the
ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input
signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up initialization
sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [tXPR=max(tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
REV 1.1
08 / 2010
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11 Page | ||
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