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K4B1G0846G Schematic ( PDF Datasheet ) - Samsung

Teilenummer K4B1G0846G
Beschreibung 1Gb G-die DDR3 SDRAM
Hersteller Samsung
Logo Samsung Logo 




Gesamt 30 Seiten
K4B1G0846G Datasheet, Funktion
Rev. 1.1, Aug. 2011
K4B1G0446G
K4B1G0846G
1Gb G-die DDR3 SDRAM
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
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may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2011 Samsung Electronics Co., Ltd. All rights reserved.
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K4B1G0846G Datasheet, Funktion
K4B1G0446G
K4B1G0846G
datasheet
3. Package pinout/Mechanical Dimension & Addressing
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package
Rev. 1.1
DDR3 SDRAM
1
2
3 456 7
8
9
A VSS
VDD
NC
B VSS VSSQ DQ0
C VDDQ DQ2 DQS
D VSSQ NC DQS
E
VREFDQ
VDDQ
NC
F NC VSS RAS
G ODT VDD CAS
H NC CS WE
J
VSS
BA0
BA2
K VDD
A3
A0
L VSS
A5
A2
M VDD
A7
A9
N VSS RESET A13
NC
DM
DQ1
VDD
NC
CK
CK
A10/AP
NC
A12/BC
A1
A11
NC
VSS
VSSQ
DQ3
VSS
NC
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
Ball Locations (x4)
Populated ball
Ball not populated
Top view
(See the balls through the package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
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6 Page









K4B1G0846G pdf, datenblatt
K4B1G0446G
K4B1G0846G
datasheet
Rev. 1.1
DDR3 SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address
Symbol
Parameter
DDR3-800/1066/1333/1600
Min.
Max.
DDR3-1866
Min.
Max.
Unit NOTE
VIH.CA(DC100) DC input logic high
VREF + 100
VDD
VREF + 100
VDD mV 1,5
VIL.CA(DC100) DC input logic low
VSS
VREF - 100
VSS
VREF - 100
mV 1,6
VIH.CA(AC175) AC input logic high
VREF + 175
Note 2
-
- mV 1,2,7
VIL.CA(AC175) AC input logic low
Note 2
VREF - 175
-
- mV 1,2,8
VIH.CA(AC150) AC input logic high
VREF+150
Note 2
-
- mV 1,2,7
VIL.CA(AC150) AC input logic low
Note 2
VREF-150
-
- mV 1,2,8
VIH.CA(AC135) AC input logic high
-
-
VREF + 135
Note 2
mV 1,2,7
VIL.CA(AC135) AC input logic low
-
-
Note 2
VREF - 135
mV 1,2,8
VIH.CA(AC125) AC input logic high
-
-
VREF+125
Note 2
mV 1,2,7
VIL.CA(AC125) AC input logic low
-
-
Note 2
VREF-125
mV 1,2,8
VREFCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V 3,4
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See ’Overshoot/Undershoot Specification’ on page 19.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is
used when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used
when VREF - 150mV is referenced.
[ Table 8 ] Single-ended AC & DC input levels for DQ and DM
Symbol
Parameter
DDR3-800/1066
Min.
Max.
DDR3-1333/1600
Min.
Max.
DDR3-1866
Min.
Max.
Unit NOTE
VIH.DQ(DC100) DC input logic high
VREF + 100
VDD
VREF + 100
VDD
VREF + 100
VDD
mV 1,5
VIL.DQ(DC100) DC input logic low
VSS VREF - 100 VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.DQ(AC175) AC input logic high
VREF + 175
NOTE 2
-
-
-
- mV 1,2,7
VIL.DQ(AC175) AC input logic low
NOTE 2
VREF - 175
-
-
-
- mV 1,2,8
VIH.DQ(AC150) AC input logic high
VREF + 150
NOTE 2
VREF + 150
NOTE 2
-
- mV 1,2,7
VIL.DQ(AC150) AC input logic low
NOTE 2
VREF - 150
NOTE 2
VREF - 150
-
- mV 1,2,8
VIH.DQ(AC135) AC input logic high
-
-
-
-
VREF + 135
NOTE 2
mV 1,2,7
VIL.DQ(AC135) AC input logic low
-
-
-
-
NOTE 2
VREF - 135 mV 1,2,8
VREFDQ(DC)
Reference Voltage for DQ,
DM inputs
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See ’Overshoot/Undershoot Specification’ on page 19.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used
when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when
VREF - 150mV is referenced.
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