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TM035KDH04 Schematic ( PDF Datasheet ) - Tianma

Teilenummer TM035KDH04
Beschreibung Display Module
Hersteller Tianma
Logo Tianma Logo 




Gesamt 24 Seiten
TM035KDH04 Datasheet, Funktion
Model No.TM035KDH04
MODEL NO. :
ISSUED DATE:
VERSION :
TM035KDH04
2013-12-5
2.3
Preliminary Specification
Final Product Specification
Customer :
Approved by
Notes
TIANMA Confirmed :
Prepared by
Checked by
Approved by
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of TIANMA MICRO-ELECTRONICS Corporation
and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of
TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 24






TM035KDH04 Datasheet, Funktion
35 D23
I
36 HSYNC
I
37 VSYNC
I
38 CLK
I
39 NC
-
40 NC
-
41 VDD
P
42 VDD
P
43 SPENA
I
44 NC
-
45 NC
-
46 NC
-
47 NC
-
48 NC
-
49 SPCK
I
50 SPDA I/O
51 NC
-
52 DEN
I
53 GND
P
54 GND
P
I: input
O: output
Note 2-1:
Mode
CCIR 656
CCIR 601
8 Bit RGB
D(23:16)
D(23:16)
D(23:16)
D(23:16)
D(15:8)
GND
GND
GND
24 Bit RGB R(7:0)
G(7:0)
Data 23
Model No.TM035KDH04
Note 2-1
Horizontal Synchronous Signal
Vertical Synchronous Signal
Data Clock
No Connect
No Connect
power supply
power supply
Serial port data enable signal
No Connect
No Connect
No Connect
No Connect
No Connect
SPI Serial Clock
SPI Serial Data Input/output
No Connect
Data enabling signal
Ground
P: power
Ground
D(7:0)
GND
GND
GND
B(7:0)
HSYNC
NC
HSYNC
HSYNC
HSYNC
VSYNC
NC
VSYNC
VSYNC
VSYNC
DEN
NC
NC
NC for HV mode
DEN for DEN mode
NC for HV mode
DEN for DEN mode
The information contained herein is the exclusive property of TIANMA MICRO-ELECTRONICS Corporation
and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of
TIANMA MICRO-ELECTRONICS Corporation.
Page 6 of 24

6 Page









TM035KDH04 pdf, datenblatt
Model No.TM035KDH04
5.4 CCIR601
Parameter
Symbol Min Typ Max Unit
CLK Frequency
Fclk
--
24.54/
27
30
MHz
CLK Cycle Time
Time From HSYNC to1 st
data input(PAL)
Time From HSYNC to1 st
data input(NTSC)
Tclk
Ths
Ths
-- 40/37 -- ns
128 264 -- CLK
128 244 -- CLK
Condition
VCC=3.0V~3.6V
DDLY = 136, Offset = 128 (fixed)
DDLY = 116, Offset = 128 (fixed)
5.5 CCIR656
Parameter
CLK Frequency
CLK Cycle Time
Time that EVA
to 1’st data input(PAL)
Symbol Min Typ Max Unit
Condition
Fclk -- 27 30 MHz
VCC=3.0V~3.6V
Tclk -- 37
Ths 128 288
-- ns
--
CLK
DDLY = 152, Offset = 128
(fixed)
The information contained herein is the exclusive property of TIANMA MICRO-ELECTRONICS Corporation
and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of
TIANMA MICRO-ELECTRONICS Corporation.
Page 12 of 24

12 Page





SeitenGesamt 24 Seiten
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