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PDF SN8P1929 Data sheet ( Hoja de datos )
| Número de pieza | SN8P1929 | |
| Descripción | 8-Bit Micro-Controller | |
| Fabricantes | SONiX | |
| Logotipo |  |
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SN8P1929
8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC
SN8P1929
USER’S MANUAL
Preliminary Specification Version 0.2
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Page 1
Preliminary Version 0.1
1 page  
SN8P1929
8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC
6.1 OVERVIEW..................................................................................................................................... 61
6.2 INTEN INTERRUPT ENABLE REGISTER................................................................................... 61
6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 63
6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 63
6.5 PUSH, POP ROUTINE .................................................................................................................... 65
6.6 INT0 (P0.0) INTERRUPT OPERATION......................................................................................... 66
6.7 INT1 (P0.1) INTERRUPT OPERATION......................................................................................... 67
6.8 T0 INTERRUPT OPERATION ....................................................................................................... 68
6.9 TC0 INTERRUPT OPERATION..................................................................................................... 69
6.10 TC1 INTERRUPT OPERATION..................................................................................................... 70
6.11 MULTI-INTERRUPT OPERATION............................................................................................... 71
77 I/O PORT ................................................................................................................................................ 73
7.1 I/O PORT MODE ............................................................................................................................. 73
7.2 I/O PULL UP REGISTER ................................................................................................................ 74
7.3 I/O PORT DATA REGISTER .......................................................................................................... 75
88 TIMERS .................................................................................................................................................. 76
8.1 WATCHDOG TIMER (WDT) ......................................................................................................... 76
8.2 TIMER 0 (T0) ................................................................................................................................... 78
8.2.1 OVERVIEW .............................................................................................................................. 78
8.2.2 T0M MODE REGISTER........................................................................................................... 79
8.2.3 T0C COUNTING REGISTER................................................................................................... 80
8.2.4 T0 TIMER OPERATION SEQUENCE ..................................................................................... 81
8.3 TIMER/COUNTER 0 (TC0) ............................................................................................................ 82
8.3.1 OVERVIEW .............................................................................................................................. 82
8.3.2 TC0M MODE REGISTER ........................................................................................................ 83
8.3.3 TC1X8, TC0X8, TC0GN FLAGS .............................................................................................. 84
8.3.4 TC0C COUNTING REGISTER ................................................................................................ 85
8.3.5 TC0R AUTO-LOAD REGISTER .............................................................................................. 87
8.3.6 TC0 CLOCK FREQUENCY OUTPUT (BUZZER) .................................................................. 88
8.3.7 TC0 TIMER OPERATION SEQUENCE .................................................................................. 89
8.4 TIMER/COUNTER 1 (TC1) ............................................................................................................ 91
8.4.1 OVERVIEW .............................................................................................................................. 91
8.4.2 TC1M MODE REGISTER ........................................................................................................ 92
8.4.3 TC1X8, TC0X8, TC0GN FLAGS .............................................................................................. 93
8.4.4 TC1C COUNTING REGISTER ................................................................................................ 94
8.4.5 TC1R AUTO-LOAD REGISTER .............................................................................................. 96
8.4.6 TC1 CLOCK FREQUENCY OUTPUT (BUZZER) .................................................................. 97
8.4.7 TC1 TIMER OPERATION SEQUENCE .................................................................................. 98
SONiX TECHNOLOGY CO., LTD
Page 5
Preliminary Version 0.1
5 Page 
SN8P1929
8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC
1.5 PIN DESCRIPTIONS
PIN NAME TYPE
DESCRIPTION
VDD, VSS, AVSS P Power supply input pins for digital / analog circuit.
VLCD
P LCD Power supply input
AVDDR
P Regulator power output pin, Voltage=3.8V.
AVE+
P
Regulator output =3.0V /2.4V/1.5V for Sensor. Maximum output current=10
mA
ACM
P Band Gap Voltage output =1.2V
AVDDCP
P
Charge Pump Voltage output. ( connect a 10uF or higher capacitor to
ground)
R+ AI Positive reference input
R- AI Negative reference input
X+ AI Positive ADC differential input, a 0.1uF capacitor connect to pin X-
X- AI Negative ADC differential input
AI1+,AI2+
AI Positive analog input channel
AI-, AI2-
AI Negative analog input channel
C+ A Positive capacitor terminal for charge pump regulator
C- A Negative capacitor terminal for charge pump regulator
VPP/ RST
OTP ROM programming pin.
P, I System reset input pin. Schmitt trigger structure, active “low”, normal stay to
“high”.
XIN, XOUT I, O External High clock oscillator pins. No RC mode
P0.0 / INT0
I
P0.0 shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up
resisters.
P0.1 / INT1
I
P0.1 shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up
resisters.
P1 [3:0]
I/O P1.0 ~ P1.3 bi-direction pins / wakeup pins/ Built-in pull-up resisters.
P2 [1:0]
I/O
P2.0 ~ P2.1 bi-direction pins / Built-in pull-up resisters. Shared with
XIN/XOUT
P4 [2:0]
I/O bi-direction pins / Built-in pull-up resisters
P5 [2:0]
I/O bi-direction pins / Built-in pull-up resisters.
P5 [4:3]
I/O bi-direction pins / Built-in pull-up resisters / Shared with PWM, TCOUT
LBTIN1/2
I Low BatTery detect Input pins shared with P4.1, P4.2
COM [3:0]
O COM0~COM3 LCD driver common port
SEG0 ~ SEG23 O LCD driver segment pins.
SONiX TECHNOLOGY CO., LTD
Page 11
Preliminary Version 0.1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SN8P1929.PDF ] | |
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