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HD1-15530-9 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HD1-15530-9
Beschreibung CMOS Manchester Encoder-Decoder
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 12 Seiten
HD1-15530-9 Datasheet, Funktion
HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
PDIP
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
1.25 MEGABIT/s PKG. NO.
HD1-15530-9
F24.6
HD1-15530-8
7802901JA
HD4-15530-9
J28.A
HD4-15530-8
78029013A
HD3-15530-9
E24.6
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for the
Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
VALID WORD 1
ENCODER
SHIFT CLK
2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC
10
DECODER RESET 11
GND 12
24 VCC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15
BIPOLAR
ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
HD-15530 (CLCC)
TOP VIEW
4 3 2 1 28 27 26
DECODER
CLK
5
25
SEND
DATA
NC 6
24 NC
NC 7
23 NC
BIPOLAR
ZERO IN
8
22
SYNC
SELECT
BIPOLAR
ONE IN
9
21
ENCODER
ENABLE
UNIPOLAR
DATA IN
10
20
SERIAL
DATA IN
DECODER
SHIFT CLK
11
19
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 2960.1






HD1-15530-9 Datasheet, Funktion
HD-15530
MIL-STD-1553
The 1553 standard defines a time division multiplexed data
bus for application within aircraft. The bus is defined to be
bipolar, and encoded in a Manchester II format, so no DC
component appears on the bus. This allows transformer
coupling and excellent isolation among systems and their
environment.
The HD-15530 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in Figure
1. Bipolar inputs from the bus, like Figure 2, are also accom-
modated.
The signaling format in MlL-STD-1553 is specified on the
assumption that the network of 32 or fewer terminals are
controlled by a central control unit by means of Command
Words. Terminals respond with Status Words. Each word is
preceded by a synchronizing pulse, and followed by parity
bit, occupying a total of 20µs. The word formats are shown in
Figure 4. The special abbreviations are as follows:
P Parity, which is defined to be odd, taken across all 17
bits.
R/T Receive on logical zero, transmit on ONE.
ME Message Error if logical 1.
TF Terminal Flat, if set, calls for controller to request
self-test data.
The paragraphs above are intended only to suggest the
content of MlL-STD-1553, and do not completely describe its
bus requirements, timing or protocols.
BUS
“1”
“0”
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
+
-
“1” REF
“0” REF
-
+
“1”
“0”
BUS
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
COMMAND
SYNC
DATA
SYNC
BIT
PERIOD
BIT
PERIOD
BIT
PERIOD
LOGICAL ONE DATA
LOGICAL ZERO DATA
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
COMMAND WORD (FROM CONTROLLER TO TERMINAL)
SYNC
5
TERMINAL
ADDRESS
15
SUB ADDRESS
/MODE
R/T
5
DATA WORD
COUNT
1
P
DATA WORD (SENT EITHER DIRECTION)
16
SYNC
CONTROL WORD
1
P
STATUS WORD (FROM TERMINAL TO CONTROLLER)
SYNC
5
TERMINAL
ADDRESS
1 9 11
CODE FOR FAILURE MODES TF P
ME
FIGURE 9. MIL-STD-1553 WORD FORMATS
NOTE: This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15530.
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HD1-15530-9 pdf, datenblatt
Die Characteristics
DIE DIMENSIONS:
155 x 195 x 19mils
METALLIZATION:
Type: Si-Al
Thickness: 11kÅ ±2kÅ
HD-15530
GLASSIVATION:
Type: SiO2
Thickness: 8kA ±1kÅ
WORST CASE CURRENT DENSITY:
1.8 x 105 A/cm2
Metallization Mask Layout
TAKE DATA
SERIAL DATA OUT
ENCODER
SHIFT CLK
HD-15530
VALID VCC
WORD
ENCODER CLK
SEND CLK IN
DECODER CLK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
SEND DATA
SYNC SELECT
ENCODER ENABLE
SERIAL DATA IN
BIPOLAR ONE OUT
OUTPUT INHIBIT
COMMAND/DATA SYNC
DECODER
RESET
GND MASTER
RESET
÷ 6 OUT
BIPOLAR ZERO OUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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