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PDF HD-0300M3-FH Data sheet ( Hoja de datos )
| Número de pieza | HD-0300M3-FH | |
| Descripción | 3 dB 90 Card Couplers | |
| Fabricantes | Hirose Electric | |
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HD-15531/883
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Support of MIL-STD-1553
• Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec
• Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec
• Variable Frame Length to 32-Bits
• Sync Identification and Lock-In
• Separate Manchester II Encode, Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
The Intersil HD-15531/883 is a high performance CMOS
device intended to service the requirements of MIL-STD-
1553 and similar Manchester II encoded, time division multi-
plexed serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections oper-
ate independently of each other, except for the master reset
and word length functions. This circuit provides many of the
requirements of MIL-STD-1553. The Encoder produces the
sync pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes the sync pulse and identi-
fies it as well as decoding the data bits and checking parity.
The HD-15531/883 also surpasses the requirements of MIL-
STD-1553 by allowing the word length to be programmable
(from 2 to 28 data bits). A frame consists of three bits for
sync followed by the data word (2 to 28 data bits) followed by
one bit of parity, thus, the frame length will vary from 6 to 32
bit periods. This chip also allows selection of either even or
odd parity for the Encoder and Decoder separately.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MIL-STD-1553 over both temperature and
voltage. For high speed applications the 15531B will support
a 2.5 Megabit/sec data rate.
The HD-15531/883 can also be used in many party line digi-
tal data communications applications, such as a local area
network or an environmental control system driven from a
single twisted pair or fiber optic cable throughout a building.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
1.25MBIT/SEC
-55oC to +125oC
HD1-15531/883
2.5MBIT/SEC
HD1-15531B/883
PKG. NO.
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-170
File Number 2962.1
1 page  
HD-15531/883
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
PARAMETER SYMBOL
(NOTE 2)
CONDI-TIONS
GROUP A
SUB-
GROUPS
TEMPERATURE
Encoder Data
Rate
FED VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Master Reset
Pulse Width
TMR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Shift Clock
Delay
TE1 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Serial Data
Setup
TE2 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Serial Data
Hold
TE3 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Enable Setup
Enable Pulse
Width
TE4 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
TE5 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Sync Setup
Sync Pulse
Width
TE6 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
TE7 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Send Data
Delay
TE8 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Bipolar Output TE9 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Delay
Enable Hold
Sync Hold
TE10
TE11
VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
DECODER TIMING
Decoder
Clock
Frequency
FDC VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Decoder
Sync Clock
FDS VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Decoder Data
Rate
FDD VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Decoder Re-
set Pulse
Width
TDR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Decoder Re-
set Setup
Time
TDRS VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Decoder Re-
set Hold Time
TDRH
VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Master Reset
Pulse
TMR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Bipolar Data
Pulse Width
TD1 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
One Zero
Overlap
TD3 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
Sync Delay
(ON)
TD6 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC
HD-15531/883
MIN MAX
- 1.25
HD-15531B/883
MIN MAX UNITS
- 2.5 MHz
150 - 150 - ns
- 125 - 80 ns
75 - 50 - ns
75 - 50 - ns
90 - 90 - ns
100 - 100 - ns
55 - 55 - ns
150 - 150 - ns
0 50 0 50 ns
- 130 - 130 ns
10 - 10 - ns
95 - 95 - ns
- 15 - 30 MHz
- 2.5 - 5.0 MHz
- 1.25 - 2.5 MHz
150 - 150 - ns
75 - 75 - ns
10 - 10 - ns
150 - 150 - ns
TDC +10
(Note 1)
-
-20
- TDC +10 -
(Note 1)
TDC-10 - TDC-10
(Note 1)
(Note 1)
110 -20 110
ns
ns
ns
5-174
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