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Teilenummer | TSA5059 |
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Beschreibung | 2.7GHz I2C-bus controlled low phase noise frequency synthesizer | |
Hersteller | Philips | |
Logo | ||
Gesamt 24 Seiten INTEGRATED CIRCUITS
DATA SHEET
TSA5059
2.7 GHz I2C-bus controlled
low phase noise frequency
synthesizer
Preliminary specification
File under Integrated Circuits, IC02
1999 Oct 05
Philips Semiconductors
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
Preliminary specification
TSA5059
Four open-collector output ports are provided on the IC for
general purpose; three of these can also be used as input
ports. A 3-bit ADC is also available.
The TSA5059 is controlled via the two-wire I2C-bus.
For programming, there is one 7-bit module address and
the R/W bit for selecting READ or WRITE mode. To be
able to have more than one synthesizer in an I2C-bus
system, one of four possible addresses is selected
depending on the voltage applied at pin AS (see Table 3).
The TSA5059 fulfils the fast mode I2C-bus, according to
the Philips I2C-bus specification. The I2C-bus interface is
designed in such a way that pins SCL and SDA can be
connected either to 5 or to 3.3 V pulled-up I2C-bus lines,
allowing the PLL synthesizer to be connected directly to
the bus lines of a 3.3 V microcontroller.
WRITE mode: R/W = 0
After the address transmission (first byte), data bytes can
be sent to the device (see Table 1). Four data bytes are
needed to fully program the TSA5059. The bus transceiver
has an auto-increment facility that permits programming of
the TSA5059 within one single transmission
(address + 4 data bytes).
The TSA5059 can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or byte 4. The meaning of the bits in the data bytes
is given in Table 1. The first bit of the first data byte
transmitted indicates whether byte 2 (first bit is logic 0) or
byte 4 (first bit is logic 1) will follow. Until an I2C-bus STOP
condition is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
To allow a smooth frequency sweep for fine tuning, and
while the data of the dividing ratio of the main divider is in
data bytes 2, 3 and 4, it is necessary for changing the
frequency to send the data bytes 2 to 5 in a repeated
sending, or to finish an incomplete transmission by a
STOP condition. Repeated sending of data bytes 2 and 3
without ending the transmission does not change the
dividing ratio. To illustrate, the following data sequences
will change the dividing ratio:
• Bytes 2, 3, 4 and 5
• Bytes 4, 5, 2 and 3
• Bytes 2, 3, 4 and STOP
• Bytes 4, 5, 2 and STOP
• Bytes 2, 3 and STOP
• Bytes 2 and STOP
• Bytes 4 and STOP.
Table 1 Write data format
BYTE
DESCRIPTION
MSB(1)
LSB CONTROL BIT
1 address
1
2 programmable divider 0
3 programmable divider N7
4 control data
1
5 control data
C1
1 0 0 0 MA1 MA0 0
N14 N13 N12 N11 N10 N9 N8
N6 N5 N4 N3 N2 N1 N0
N16 N15 PE R3 R2 R1 R0
C0 XCE XCS P3 P2/T2 P1/T1 P0/T0
A
A
A
A
A
Note
1. MSB is transmitted first.
1999 Oct 05
6
6 Page Philips Semiconductors
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
Preliminary specification
TSA5059
CHARACTERISTICS
VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; fxtal = 4 MHz; measured according to Fig.4; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supply (pin VCC)
VCC
ICC
VCC(POR)
supply voltage
supply current
Tamb = 25 °C
supply voltage below which POR is active Tamb = 25 °C
RF inputs (pins RFA and RFB)
4.5 5.0 5.5
30 37 45
− 2.75 −
V
mA
V
fi(RF)
Vi(RF)(rms)
RF input frequency
RF input voltage (RMS value)
Zi(RF)
Ci(RF)
MDR
RF input impedance
RF input capacitance
main divider ratio
fi(RF) between 64 and
150 MHz; note 1
fi(RF) between 150 and
2200 MHz; note 1
fi(RF) between 2.2 and
2.7 GHz; note 1
see Fig.7
see Fig.7
prescaler disabled
prescaler enabled
64
12.6
−25
7.1
−30
22.4
−20
−
−
64
128
−
−
−
−
−
−
−
−
−
−
−
2700 MHz
300 mV
+2.5 dBm
300 mV
+2.5 dBm
300 mV
+2.5 dBm
−Ω
− pF
131 071
262 142
Crystal oscillator (pin XTAL)
fxtal
ZXTAL
ZXTAL
PXTAL
fi(ext)
Vi(ext)(p-p)
crystal frequency
crystal oscillator negative impedance
recommended crystal series resistance
crystal drive level
external reference input frequency
external reference input voltage
(peak-to-peak value)
4 MHz crystal
4 MHz crystal
4 MHz crystal; note 2
note 3
note 3
4
400
−
−
2
200
− 16
680 −
− 200
40 −
− 20
− 500
MHz
Ω
Ω
µW
MHz
mV
Phase comparator and charge pump
fcomp
Ncomp
Icp
Icpl
comparison frequency
equivalent phase noise at the phase
detector input
charge pump current
charge pump leakage current
fcomp = 250 kHz;
C1 = C0 = 1;
in the loop bandwidth
C1 = 0; C0 = 0
C1 = 0; C0 = 1
C1 = 1; C0 = 0
C1 = 1; C0 = 1
−
−
100
210
450
920
−10
−2
−157 −
MHz
dBc/Hz
135
280
600
1 230
0
170
350
750
1 540
+10
µA
µA
µA
µA
nA
1999 Oct 05
12
12 Page | ||
Seiten | Gesamt 24 Seiten | |
PDF Download | [ TSA5059 Schematic.PDF ] |
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