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PDF AR6103 Data sheet ( Hoja de datos )
| Número de pieza | AR6103 | |
| Descripción | ROCm Integrated 802.11n | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
November 2010
AR6103 ROCmTM Integrated 802.11n
General Description
The AR6103 is a complete, small form factor
802.11 b/g/n Wi-Fi solution optimized for low-
power, low-cost, and highly integrated mobile
and portable consumer electronic devices. The
device integrates all Wi-Fi functionality in a
package friendly to low-cost PCB design,
requiring only a few external bypass capacitors
and connection to an antenna.
The AR6103 is part of the 3rd generation
ROCm™ family of mobile 11n devices,
employing the world's lowest power
consumption embedded architecture.
The AR6103 can support numerous external
Bluetooth devices, and includes advanced PTA
coexistence support. A flexible architecture
enables optional customization to meet
customer specific profiles and use cases.
Atheros Confidential
AR6103 Block Diagram
On-chip high-efficiency high-output EPA™
power amplifier with zero calibration,
integrated LNAs, integrated receive and
transmit RF matching circuits, integrated
reference crystal, and integrated T/R switch
eliminate the need for external RF components
and enable direct antenna connection.
Ultra low power consumption radio
architecture and proprietary power save
technologies extend battery life. On-chip high-
efficiency PMU (power management unit)
enables direct-connect to battery, eliminating
the need for external regulators. An on-chip
embedded CPU handles complete 11n
processing to minimize host processor loading.
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®,
Super G®, Total 802.11®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air is
Cleaner at 5-GHz™, XSPAN®, Wireless Future. Unleashed Now.®, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
PRELIMINARY: ATHEROS CONFIDENTIAL
•1
1 page  
1. Features Summary
1.1 Overview
The AR6103 power management engine
The AR6103 is a single package combination
IEEE 802.11 (b, g, n) based on cutting edge
technology from the AR6003 ROCm™ family
of mobile 11n. The AR6103 contains 802.11
including full digital MAC and baseband
engines handling all 802.11b (CCK), 11g/n
(OFDM). An embedded low-power CPU cores
utilizes advanced power save techniques such
as: gating clocks to idle or inactive blocks,
voltage scaling to specific blocks in certain
states, fast start and settling circuits to reduce
Tx and active duty cycles, CPU frequency
scaling, and other techniques to optimize
power consumption across all operation states.
minimize host loading and maximize flexibility
to support customer specific profiles and use
1.4 Manufacturing Calibration
cases.
sThe AR6103 is architected for ultra-low power
ticconsumption, with near zero power
risconsumption in idle and stand-by modes,
te tialenabling users to leave Wi-Fi "always on".
c nA pin-compatible standalone 802.11n plus
ra eadvanced Bluetooth device (AR6133) is also
ha fidavailable.
C on1.2 Radio Front End
ce CThe AR6103 features a high-power high-
an rosefficiency on-chip power amplifier that
features the following:
rform the■ Atheros proprietary EPA™ linearization
Atechnology for Wi-Fi.
e -■ Highly integrated LNAs .
: P ge■ Integrated receive and transmit RF
ry nmatching and switching enable direct
ina haantenna connection with high performance,
Clow power consumption, and near-zero
lim toRBOM for lowest solution cost.
re ct1.3 Power Management
P jeThe AR6103 features direct connection to
ubbattery, eliminating the need for external
Sregulators and/or PMU. The AR6103
The AR6103 utilizes internal self-calibration
and BIST (built-in self test) circuits to maintain
optimal performance over temperature, time
and process variation. The AR6103 is delivered
fully tested and does not require any customer
manufacturing line calibration.
1.5 Internal One-Time Programmable
Memory
The AR6103 includes internal one-time
programmable memory which may be used to
store the device MAC address, eliminating the
need for external EEPROM.
1.6 Reference Frequency
The AR6103 incorporates an on-chip 26MHz
(20ppm) reference frequency source.
Internally, the system reference frequency is
sleep regulated and gated to enable the internal
crystal to be powered down when the device is
in sleep mode. Manufacturing calibration of
the crystal is not required, but is supported as
an option.
1.7 Internal Sleep Clock
The AR6103 incorporates integrated on-chip
low power sleep clocks to regulate internal
timing, eliminating the need for any external
supports operating voltage from 4.2V down to
32kHz real time clocks or crystal oscillators.
3.1V and is tolerant of momentary overvoltage
up to 5.5V. An on-chip switching regulator
1.8 Interfaces
supports PWM mode and burst mode to
optimize power efficiency under both peak
operation and low load conditions. An internal
The AR6103 supports SDIO 1.x and the latest
2.0 standard.
PMU with separate analog and digital LDO
regulation provides superior noise isolation for
1.8.1 Standard Host Interface
analog and digital supplies.
The AR6103 supports industry standard SDIO
An optional PMU bypass mode, disables the
on-chip switching regulator to allow an
2.0 (50MHz, 4-bit and 1-bit) and GSPI (Generic
SPI) for Wi-Fi.
external 1.8V regulated supply to directly
power the device, if so desired.
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
AR6103 ROCm® Data Sheet •
5
November 2010 • 5
5 Page 
■ A small linear regulator (SREG) which
converts the host IO supply to a 1.2V supply
for some small control blocks which are
turned on when CHIP_PWD_L is de-
asserted.
■ A larger linear regulator (DREG) which
converts the 1.8V input to 1.2V for the bulk
of AR6103 core digital circuitry. The input is
typically connected to the SWREG output.
■ A linear regulator (PAREG) which converts
the battery input to a 3.3V supply that can
be used for the antenna switch controls as
well as the internal AR6103 EPA.
In applications where external supplies are
already present, the AR6103 supports
bypassing all supplies generated by the PMU.
WAKEUP state, wait for the reference clock
source to stabilize, and then ungate all enabled
clock trees. The CPU wakes up only when an
interrupt arrives, which may have also
generated the system WAKEUP event.
Figure 2-1 depicts the state transition diagram.
2.11 Power Transition Diagram
The AR6103 provides integrated power
management and control functions and
extremely low power operation for maximum
battery life across all operational states by:
■ Gating clocks for logic when not needed
■ Shutting down unneeded high speed clock
sources
■ Reducing voltage levels to specific blocks in
some states
When the AR6103 is in a low power state, the
Tswitching power supply (SWREG) as well as
the main 1.2V regulator for digital circuits
O(DREG) are both turned off. All digital circuits
that normally rely upon 1.2V power from
NDREG are switched to use power from the
smaller SREG regulator using a "Make-and-
Break" mechanism.
DO2.11.1 Hardware Power States
AR6103 hardware has five top level hardware
power states managed by the RTC block.
Table 2-1 describes the input from the MAC,
CPU, SDIO/MBOX, interrupt logic, and timers
that affect the power states.
2.11.2 Sleep State Management
Sleep state minimizes power consumption
while saving system states. In SLEEP state, all
high speed clocks are gated off and the external
reference clock source is powered off. The
SWREG, DREG, and PAREG supplies are also
turned off during SLEEP. For the AR6103 to
enter SLEEP state, the MAC, MBOX, and CPU
systems must not be active.
The system remains in sleep state until a
WAKEUP event causes the system to enter
COPY
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
AR6103 ROCm® Data Sheet • 11
November 2010 • 11
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet AR6103.PDF ] | |
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