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G2216-208-041PFB2 Schematic ( PDF Datasheet ) - GlobespanVirata

Teilenummer G2216-208-041PFB2
Beschreibung Transceiver
Hersteller GlobespanVirata
Logo GlobespanVirata Logo 




Gesamt 30 Seiten
G2216-208-041PFB2 Datasheet, Funktion
June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
XDSL2TM SDSL, HDSL2, or SHDSL - ILD2
Dual-Channel, Low Power, Programmable
Transceiver with Integrated Framer and Line Drivers
Data Sheet
Overview
The GlobespanVirata® XDSL2™ Digital Subscriber Line
(DSL) chip sets provide low power, high density solutions for
2-wire DSL equipment. These chip sets are fully
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new network services. The GlobespanVirata® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
(ILD2).
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channels into a standard interface. GlobespanVirata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 dual-channel DSL chip sets are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Features
Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
Two AFEs, each with an integrated differential line driver
2B1Q, CAP, or PAM line codes
Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
Offers physical layer interoperability with competitive solu-
tions
Glueless interface to popular microprocessors
Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
Reference design compatible with Bellcore GR-1089, IEC
60950, UL 1950, ITU-T K.20 and K.21
Built-in framer provides easy access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
Interfaces directly with off-the-shelf single-channel T1/E1
transceivers
ATM UTOPIA Level 1 and 2 interface
A single oscillator and hybrid topology supports all speeds
+3.3V and +5V power supplies
Customer Interface
TDATA (A/B)
TClock (A/B)
Frame Pulse (A/B)
RDATA (A/B)
Rclock (A/B)
Frame Pulse (A/B)
Dual
Channel
DSP
w/Framer
µ Processor Interface
ILD2
ILD2
Figure 1. Block Diagram of XDSL2™ DSP with Two Single-Channel ILD2s
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2






G2216-208-041PFB2 Datasheet, Funktion
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
System Power Requirements
The 144-pin Dual-channel DSP/Framer chip requires +3.3V (see Table 14 on page 16 for tolerance), and the two
ILD2 chips require +3.3V (±5%) as well as +5V (±5%). Power requirements, including transceiver power
consumption, have a tolerance of ±5%. The maximum peak-to-peak ripple and noise voltage is 50 mV for all
supplies.
The transceiver obtains its power from the power feed in the Host through the power interface. Table 3, Table 4,
Table 5, and Table 7 provide power requirements for the 144-pin Dual-channel DSP.
Table 3. Typical SDSL 2B1Q System Power Consumption
Per Channel (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
144
272
400
528
784
1040
1168
1552
2064
2320
Drain Current (mA)
3.3VD
DSP & ILD2
75
105
110
115
160
170
210
235
250
280
5VA
ILD2
85
85
90
90
90
90
90
95
95
95
Power/Port
(mW)
673
772
813
830
978
1011
1143
1251
1300
1400
Table 4. Typical SDSL CAP System Power Consumption
Per Channel (DSP/Framer in a 144 TQFP)
Line Rate
(Kb/s)
144
272
400
528
784
1040
1552
2064
2320
Drain Current (mA)
3.3VD
DSP & ILD2
75
80
115
145
145
145
155
165
185
5VA
ILD2
90
90
105
115
115
115
115
120
120
Power/Port
(mW)
698
714
905
1055
1055
1055
1087
1145
1210
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-02 using 1:2 transformer
Add 30 mA at 5VA for unified designs based on
SHDSL population option G-02-2302-1006C-03
using 1:4 transformer or HDSL2 population option
G-02-2302-1006C-03 using 1:5.4 transformer
3. Transmit power: 13.5 dbm (nominal at all rates)
4. Measured during activation and data mode
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-03 using 1:4 transformer
3. Transmit power: 13.5 dbm (nominal at 2320kb/s)
4. Measured during activation and data mode
GlobespanVirata, Inc. — Proprietary
6
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

6 Page









G2216-208-041PFB2 pdf, datenblatt
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s)
Mode(s)
Functional Description
34 BPDO2/APDO8
35 BPDO1/APDO7
36 BPDO0/APDO6
37 VDD
O
Master Clock to ILD2, Channel B. Input to AFE PLL which generates oversampling clocks. Connected
to ILD2 pin MCLK for channel B.
O
Control Output, Channel B. Control signal transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin
CSD for channel B.
O
Data Out, Channel B. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACA for
channel B.
P +3.3V supply.
38 D2ACKB
O Not used for this application. Per application schematic, do not connect.
SERIAL
I/O No Connect. For serial interface applications, this pin is used for debug purposes only.
39
XSB0B/TXA2
UTOPIA
TXA2- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
I/O appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
SERIAL
I/O No Connect. For serial interface applications, this pin is used for debug purposes only.
40
XSB1B/TXA3
UTOPIA
TXA3- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
I/O appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
SERIAL
I/O Not used for this application. Per application schematic, do not connect.
41
TXA4
UTOPIA
TXA4- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
I/O appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
42 VSS
Ground.
SERIAL
I/O Not used for this application. Per application schematic, do not connect.
43
44
45
RXA4
RXA2
RXA3
UTOPIA
ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the appropriate
I/O PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
46 INTA
47 INTB
Interrupt of DSP A. Carries interrupts from internal DSP core A. The polarity of the interrupt level is
O
programmable with default to inactive open-drain. Internally generated status can be enabled to activate
the interrupt pin. Used during start-up for code downloads. INTA and INTB are both required. Both can
be declared open-drain and tied together, if desired.
Interrupt of DSP B. Carries interrupts from internal DSP core B and framer. The polarity of the interrupt
O
level is programmable with default to inactive open-drain. Internally generated status can be enabled to
activate the interrupt pin. Used during start-up for code downloads and EOC interrupts in data mode. INTA
and INTB are both required. Both can be declared open-drain and tied together, if desired.
48 MOD2
49 MOD1
50 MOD0
Host Bus Mode. Bits 2 through 0. These input pins define the host bus control modes:
000 = Non-multiplexed processor mode
I
001 = Motorola mode where RDN is R/W and WRN is DSN
01X = reserved for testing
100 = Multiplexed processor mode
101 = reserved for testing.
51 AVDD
52 AVSS
53 VDD
P AVDD. Digital +3.3V supply for VCO.
AVSS. Ground pin for VCO. Connect to digital ground as per schematic.
P +3.3V supply.
54 VSS
55 REFCK
56 DCO
Ground.
I/O Reference Clock. Used to pass network timing reference.
I/O DCO. Pull up as per application schematic.
57 A0
58 A1
59 A2
60 A3
61 A4
62 AD0
63 AD1
64 AD2
65 AD3
66 AD4
67 AD5
68 AD6
69 AD7
Address Bus. Bits 4 through 0. Host Address bus in the non-multiplexed mode.
I A[4:3] are used to select between the two internal 8 byte address spaces.
I/O
Multiplexed Address and Data Bus.
AD[4:0] = Address inputs in multiplexed mode. See A[4:0] for usage.
GlobespanVirata, Inc. — Proprietary
12
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

12 Page





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