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PDF BUK9614-55A Data sheet ( Hoja de datos )
| Número de pieza | BUK9614-55A | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK9614-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 7 February 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive and general purpose
power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
ID
drain current
VGS = 5 V; Tmb = 25 °C;
see Figure 1; see Figure 3
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Static characteristics
RDSon
drain-source on-state VGS = 5 V; ID = 25 A; Tj = 25 °C;
resistance
see Figure 12; see Figure 13
Avalanche ruggedness
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C
VGS = 10 V; ID = 25 A;
Tj = 25 °C
EDS(AL)S
non-repetitive
drain-source
avalanche energy
ID = 73 A; Vsup ≤ 55 V;
RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
Min Typ Max Unit
- - 55 V
- - 73 A
- - 149 W
- 12 14 mΩ
- - 15 mΩ
- 11 13 mΩ
- - 230 mJ
1 page  
NXP Semiconductors
BUK9614-55A
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to
mounting base
thermal resistance from junction to
ambient
Conditions
see Figure 4
minimum footprint ; mounted
on a printed-circuit board
Min Typ Max Unit
- - 1 K/W
- 50 - K/W
10
Zth(j-mb)
(K/W)
03nd67
1
δ = 0.5
0.2
10−1 0.1
0.05
0.02
10−2
Single Shot
10−3
10−6
10−5
10−4
10−3
P
tp
δ=
T
10−2
tp
T
t
10−1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9614-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
BUK9614-55A
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
BUK9614-55A v.2
Modifications:
20110207
Product data sheet
-
BUK9514_9614_55A v.1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number BUK9614-55A separated from data sheet BUK9514_9614_55A v.1
BUK9514_9614_55A v.1 20010207
Product specification -
-
BUK9614-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 February 2011
© NXP B.V. 2011. All rights reserved.
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