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Teilenummer | PSMN3R0-30YL |
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Beschreibung | MOSFET ( Transistor ) | |
Hersteller | NXP Semiconductors | |
Logo | ||
Gesamt 15 Seiten PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
Rev. 04 — 10 March 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference data
Symbol
VDS
ID
Parameter
drain-source voltage
drain current
Conditions
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 25 °C; VGS = 10 V;
see Figure 1
Ptot total power dissipation
Tj junction temperature
Static characteristics
Tmb = 25 °C; see Figure 2
RDSon
drain-source on-state
resistance
Dynamic characteristics
VGS = 10 V; ID = 15 A;
Tj = 25 °C
QGD
gate-drain charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
QG(tot)
total gate charge
Avalanche ruggedness
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C;
drain-source avalanche ID = 100 A; Vsup ≤ 30 V;
energy
RGS = 50 Ω; unclamped
Min Typ Max Unit
- - 30 V
[1] - - 100 A
--
-55 -
81 W
175 °C
- 2.19 3 mΩ
- 5.1 - nC
- 21 - nC
- - 75 mJ
[1] Continuous current is limited by package.
NXP Semiconductors
PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
6. Characteristics
Table 6. Characteristics
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
gate-source threshold voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 12
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 13
RG gate resistance
Dynamic characteristics
VGS = 10 V; ID = 15 A; Tj = 25 °C
f = 1 MHz
QG(tot)
total gate charge
ID = 10 A; VDS = 12 V; VGS = 10 V;
see Figure 14; see Figure 15
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14
QGS
QGS(th)
gate-source charge
pre-threshold gate-source
charge
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
QGS(th-pl)
post-threshold gate-source
charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau voltage
VDS = 12 V; see Figure 14;
see Figure 15
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
Min Typ Max Unit
30 - - V
27 - - V
1.3 1.7 2.15 V
0.65 - - V
- - 2.45 V
- - 1 µA
- - 100 µA
- - 100 nA
- - 100 nA
- 3.04 4.04 mΩ
- - 5.2 mΩ
-
2.19 3
mΩ
- 0.55 1.5 Ω
- 45.8 - nC
- 43 - nC
- 21 - nC
- 7.02 - nC
- 4.74 - nC
- 2.28 - nC
- 5.1 - nC
- 2.37 - V
- 2822 - pF
- 615 - pF
- 260 - pF
- 34 - ns
- 58 - ns
- 50 - ns
- 21 - ns
PSMN3R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 10 March 2011
© NXP B.V. 2011. All rights reserved.
6 of 15
6 Page NXP Semiconductors
PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
PSMN3R0-30YL v.4
Modifications:
20110310
Product data sheet
• Various changes to content.
PSMN3R0-30YL v.3 20091228
Product data sheet
Change notice
-
-
Supersedes
PSMN3R0-30YL v.3
PSMN3R0-30YL v.2
PSMN3R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 10 March 2011
© NXP B.V. 2011. All rights reserved.
12 of 15
12 Page | ||
Seiten | Gesamt 15 Seiten | |
PDF Download | [ PSMN3R0-30YL Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
PSMN3R0-30YL | N-channel TrenchMOS logic level FET | NXP Semiconductors |
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