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| Número de pieza | PSMN7R0-30MLC | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | NXP Semiconductors | |
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PSMN7R0-30MLC
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK33 using
NextPower Technology
Rev. 4 — 15 June 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK33 package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high
system efficiencies at low and high
loads
1.3 Applications
DC-to-DC converters
Load switching
Synchronous buck regulator
1.4 Quick reference data
Table 1. Quick reference data
Symbol
Parameter
VDS drain-source voltage
ID drain current
Ptot total power dissipation
Tj junction temperature
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD gate-drain charge
QG(tot)
total gate charge
Conditions
Tj = 25 °C
Tmb = 25 °C; VGS = 10 V; see Figure 1
Tmb = 25 °C; see Figure 2
VGS = 4.5 V; ID = 15 A; Tj = 25 °C;
see Figure 10
VGS = 10 V; ID = 15 A; Tj = 25 °C;
see Figure 10
VGS = 4.5 V; ID = 15 A; VDS = 15 V;
see Figure 12; see Figure 13
VGS = 4.5 V; ID = 15 A; VDS = 15 V;
see Figure 12; see Figure 13
Min Typ Max Unit
- - 30 V
- - 67 A
- - 57 W
-55 -
175 °C
-
7.8 9
mΩ
-
6.05 7
mΩ
- 2 - nC
- 8.2 - nC
1 page  
NXP Semiconductors
PSMN7R0-30MLC
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK33 using NextPower Technology
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
VGS(th)
∆VGS(th)/∆T
IDSS
gate-source threshold
voltage
gate-source threshold
voltage variation with
temperature
drain leakage current
IGSS gate leakage current
RDSon
drain-source on-state
resistance
RG gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
QGS(th)
QGS(th-pl)
QGD
VGS(pl)
Ciss
Coss
Crss
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
Conditions
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C;
see Figure 10
VGS = 4.5 V; ID = 15 A; Tj = 150 °C;
see Figure 10; see Figure 11
VGS = 10 V; ID = 15 A; Tj = 25 °C;
see Figure 10
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 10; see Figure 11
f = 1 MHz
ID = 15 A; VDS = 15 V; VGS = 10 V;
see Figure 12; see Figure 13
ID = 15 A; VDS = 15 V; VGS = 4.5 V;
see Figure 12; see Figure 13
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 15 A; VDS = 15 V; VGS = 4.5 V;
see Figure 12; see Figure 13
ID = 15 A; VDS = 15 V;
see Figure 12; see Figure 13
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
Min Typ Max Unit
30 - - V
27 - - V
1.45 1.75 2.15 V
- -3.9 - mV/K
- - 1 µA
- - 100 µA
- - 100 nA
- - 100 nA
-
7.8 9
mΩ
- - 15.3 mΩ
-
6.05 7
mΩ
- - 11.9 mΩ
124Ω
- 17.9 - nC
- 8.2 - nC
- 16.2 - nC
- 2.9 - nC
- 1.9 - nC
- 1 - nC
- 2 - nC
- 2.72 - V
- 1076 - pF
- 248 - pF
- 88 - pF
PSMN7R0-30MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 15 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
PSMN7R0-30MLC
N-channel 30 V 7 mΩ logic level MOSFET in LFPAK33 using NextPower Technology
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
PSMN7R0-30MLC v.4
Modifications:
20120615
Product data sheet
• Status changed from objective to product.
• Various changes to content.
PSMN7R0-30MLC v.3 20120607
Objective data sheet
Change notice
-
-
Supersedes
PSMN7R0-30MLC v.3
PSMN7R0-30MLC v.2
PSMN7R0-30MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 15 June 2012
© NXP B.V. 2012. All rights reserved.
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