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Le58QL02FJC Schematic ( PDF Datasheet ) - Zarlink

Teilenummer Le58QL02FJC
Beschreibung Quad Low Voltage Subscriber Line Audio-Processing Circuit
Hersteller Zarlink
Logo Zarlink Logo 




Gesamt 66 Seiten
Le58QL02FJC Datasheet, Funktion
Le58QL02/021/031
Quad Low Voltage Subscriber Line Audio-Processing Circuit
VE580 Series
APPLICATIONS
„ Codec function on telephone switch line cards
FEATURES
„ Low-power, 3.3 V CMOS technology with 5-V tolerant
digital inputs
„ Software and coefficient compatible to the Le79Q02/
021/031 QSLAC™ device
„ Performs the functions of four codec/filters
„ Software programmable:
— SLIC device input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock edge
options
„ Standard microprocessor interface
„ A-law, µ-law, or linear coding
„ Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port
— Optional supervision on the PCM highway
„ 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or
8.192 MHz master clock derived from MCLK or PCLK
„ Built-in test modes with loopback, tone generation,
and µP access to PCM data
„ Mixed state (analog and digital) impedance scaling
„ Performance guaranteed over a 12 dB gain range
„ Real Time Data register with interrupt (open drain or
TTL output)
„ Supports multiplexed SLIC device outputs
„ Broadcast state
„ 256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
„ Maximum channel bandwidth for V.90 modems
RELATED LITERATURE
„ 080754 Le58QL061/063 QLSLAC™ Device Data Sheet
„ 080761 QSLAC™ to QLSLAC™ Device Design
Conversion Guide
„ 080758 QSLAC™ to QLSLAC™ Guide to New Designs
ORDERING INFORMATION
Device
Package (Green)1
Packing2
Le58QL02FJC
44-pin PLCC
Tube
Le58QL021FJC
44-pin PLCC
Tube
Le58QL021BVC
44-pin TQFP
Tray
Le58QL031DJC
32-pin PLCC
Tube
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2. For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
DESCRIPTION
The Le58QL02/021/031 Quad Low Voltage Subscriber Line
Audio-Processing Circuit (QLSLAC™) devices integrate the
key functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
Advanced submicron CMOS technology makes the Le58QL02/
021/031 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
Analog
VIN1
VOUT 1
VIN2
VOUT 2
VIN3
VOUT 3
VIN4
VOUT 4
VREF
SLIC
CD11
CD21
C31
C41
C51
CD12
CD22
C32
C42
C52
CD13
CD23
C33
C43
C53
CD14
CD24
C34
C44
C54
CHCLK
Signal Processing
Channel 1 (CH 1)
Signal Processing
Channel 2 (CH 2)
Signal Processing
Channel 3 (CH 3)
Signal Processing
Channel 4 (CH 4)
Clock
&
Reference
Circuits
Time Slot Assigner
(TSA)
SLIC
Interface
(SLI)
Microprocessor Interface
(MPI)
INT CS DIO DCLK
Microprocessor
Dual/Single
PCM
Highway
DXA
DRA
TSCA
DXB
DRB
TSCB
FS
PCLK
MCLK/E1
RST
Document ID# 080753 Date: April 09, 2009
Version:
9
Distribution: Public Document






Le58QL02FJC Datasheet, Funktion
Le58QL02/021/031
Data Sheet
PRODUCT DESCRIPTION
The QLSLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber line interface
circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM samples and
converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the voice signals.
All of the digital filtering is performed in digital signal processors operating from a master clock, which can be derived either from
PCLK or MCLK.
Four independent channels allow the QLSLAC device to function as four SLAC™ devices. For programming information, each
channel has its own enable bit (EC1, EC2, EC3, and EC4) to allow individual channel programming. If more than one Channel
Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written;
therefore, a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information. The
Channel Enable bits are contained in the Channel Enable (EC) register, which is written and read using Command 4A/4Bh. The
Broadcast mode is useful in initializing QLSLAC devices in a large system.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter
coefficients can be calculated using the WinSLAC™ software.
Data transmitted or received on the PCM highway can be 8-bit companded code (with an optional 8-bit signaling byte in the
transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two
consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM data is read from
and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The transmit clock edge and
clock slot can be selected for compatibility with other devices that can be connected to the PCM highway.
Three configurations of the QLSLAC device are offered with single or dual PCM highways. The Le58QL02 and Le58QL021
QLSLAC devices with dual and single PCM highways respectively are available in the 44-pin packages. The Le58QL031JC
QLSLAC device is a single PCM highway version in a 32-pin PLCC package.
Table 1. QLSLAC Device Configurations
PCM Highway
Dual
Single
Single
Programmable I/O
per Channel
Four I/O
Five I/O
Two I/O
Chopper Clock
Yes
No
No
Package
44 PLCC
44 PLCC/TQFP
32 PLCC
Part Number
Le58QL02JC
Le58QL021JC (or VC)
Le58QL031JC
BLOCK DESCRIPTIONS
Clock and Reference Circuits
This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage
for the analog circuits.
Microprocessor Interface (MPI)
This block communicates with the external control microprocessor over a serial interface. It passes user control information to
the other blocks, and it passes status information from the blocks to the user. In addition, this block contains the reset circuitry.
Time Slot Assigner (TSA)
This block communicates with the PCM highway, where the PCM highway is a time division mutiplexed bus carrying the digitized
voice samples. The block implements programmable time slots and clocking arrangements in order to achieve a first layer of
switching. Internally, this block communicates with the Signal Processing Channels (CHx).
Signal Processing Channels (CHx)
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is interfaced to the VIN
and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot Assigner (TSA) block.
SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to
operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering.
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Zarlink Semiconductor Inc.

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Le58QL02FJC pdf, datenblatt
Le58QL02/021/031
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Storage Temperature
Ambient Temperature, under Bias
Ambient relative humidity (non condensing)
VCCA with respect to AGND
VCCA with respect to VCCD
VCCD with respect to DGND
VIN with respect to AGND
AGND with respect to DGND
Digital pins with respect to DGND
Total combined CD1–C5 current per device:
Source from VCCD
Sink into DGND
Latch up immunity (any pin)
Total VCC current if rise rate of VCC > 0.4 V/µs
–60° C < TA < +125° C
–40° C < TA < +85° C
5 to 95%
–0.4 to + 4.0 V
±0.4 V
–0.4 to + 4.0 V
–0.4 V to (VCCA + 0.4 V)
±50 mV
–0.4 to 5.5 V or VCCD + 2.37 V, whichever is
smaller
40 mA
40 mA
± 100 mA
0.5 A
Package Assembly
The green package devices are assembled with enhanced environmental compatible lead (Pb), halogen, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-
free board assembly processes.
Refer to IPC/JEDEC J-Std-020 Table 4-2 for recommended peak soldering temperature and Table 5-2 for the recommended
solder reflow temperature profile.
OPERATING RANGES
Legerity guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment.
Environmental Ranges
Ambient Temperature
Ambient Relative Humidity
–40° C < TA < +85° C
15 to 85%
Electrical Ranges
Analog Supply VCCA
Digital Supply VCCD
DGND
AGND
CFIL Capacitance: VREF to AGND
Digital Pins
+3.3 V ± 5%
VCCD ± 50 mV
+3.3 V ± 5%
0V
±10 mV
0.1 µF ± 20%
DGND to +5.25 V
12
Zarlink Semiconductor Inc.

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