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PDF Le58QL031 Data sheet ( Hoja de datos )
| Número de pieza | Le58QL031 | |
| Descripción | Quad Low Voltage Subscriber Line Audio-Processing Circuit | |
| Fabricantes | Zarlink | |
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Le58QL02/021/031
Quad Low Voltage Subscriber Line Audio-Processing Circuit
VE580 Series
APPLICATIONS
Codec function on telephone switch line cards
FEATURES
Low-power, 3.3 V CMOS technology with 5-V tolerant
digital inputs
Software and coefficient compatible to the Le79Q02/
021/031 QSLAC™ device
Performs the functions of four codec/filters
Software programmable:
— SLIC device input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock edge
options
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or
8.192 MHz master clock derived from MCLK or PCLK
Built-in test modes with loopback, tone generation,
and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Real Time Data register with interrupt (open drain or
TTL output)
Supports multiplexed SLIC device outputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
Maximum channel bandwidth for V.90 modems
RELATED LITERATURE
080754 Le58QL061/063 QLSLAC™ Device Data Sheet
080761 QSLAC™ to QLSLAC™ Device Design
Conversion Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
ORDERING INFORMATION
Device
Package (Green)1
Packing2
Le58QL02FJC
44-pin PLCC
Tube
Le58QL021FJC
44-pin PLCC
Tube
Le58QL021BVC
44-pin TQFP
Tray
Le58QL031DJC
32-pin PLCC
Tube
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2. For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
DESCRIPTION
The Le58QL02/021/031 Quad Low Voltage Subscriber Line
Audio-Processing Circuit (QLSLAC™) devices integrate the
key functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
Advanced submicron CMOS technology makes the Le58QL02/
021/031 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
Analog
VIN1
VOUT 1
VIN2
VOUT 2
VIN3
VOUT 3
VIN4
VOUT 4
VREF
SLIC
CD11
CD21
C31
C41
C51
CD12
CD22
C32
C42
C52
CD13
CD23
C33
C43
C53
CD14
CD24
C34
C44
C54
CHCLK
Signal Processing
Channel 1 (CH 1)
Signal Processing
Channel 2 (CH 2)
Signal Processing
Channel 3 (CH 3)
Signal Processing
Channel 4 (CH 4)
Clock
&
Reference
Circuits
Time Slot Assigner
(TSA)
SLIC
Interface
(SLI)
Microprocessor Interface
(MPI)
INT CS DIO DCLK
Microprocessor
Dual/Single
PCM
Highway
DXA
DRA
TSCA
DXB
DRB
TSCB
FS
PCLK
MCLK/E1
RST
Document ID# 080753 Date: April 09, 2009
Version:
9
Distribution: Public Document
1 page  
Le58QL02/021/031
Data Sheet
LIST OF FIGURES
Figure 1. Le58QL02JC 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2. Le58QL021JC 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3. Le58QL031JC 32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4. Le58QL021VC 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5. Transmit Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 6. Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7. Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8. A-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9. µ-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 10. Total Distortion with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 11. Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12. Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 13. Analog-to-Analog Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 14. Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 16. Microprocessor Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 17. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . .25
Figure 18. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . .26
Figure 19. Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 20. Clock Mode Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 21. SLIC Device I/O E1 Multiplex and Real-Time Data Register Operation. . . . . . . . . . . . . . . . . . .29
Figure 22. E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 23. MPI Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 24. QLSLAC Device Transmission Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 25. Robbed-Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 26. Le7920 SLIC/QLSLAC Device Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
QLSLAC Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR . . . . . . . . . . . . . . . . .14
Channel Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Channel Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Global Chip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Global Chip Status Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
A-Law: Positive Input Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5
Zarlink Semiconductor Inc.
5 Page 
Pin Names
Type
DRA, DRB
Inputs
DXA, DXB
Outputs
FS Input
INT Output
MCLK/E1
Input/Output
PCLK
Input
RST
Input
TSCA, TSCB Outputs
VCCA, VCCD Power
VIN1–VIN4
Inputs
VOUT1–
VOUT4
Outputs
VREF
Output
Le58QL02/021/031
Data Sheet
Description
PCM Data Receive A/B. The PCM data for channels 1, 2, 3, and 4 is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear state, two consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate. DRB is not available on all package
types.
PCM Data Transmit. The transmit data from channels 1, 2, 3, and 4 is sent serially out on
either the DXA or DXB port or both ports during user-programmed time slots. Data is always
transmitted with the most significant bit first. The output is available every 125 µs and the data
is shifted out in 8-bit (16-bit in Linear or PCM Signaling state) bursts at the PCLK rate. DXA
and DXB are High impedance between time slots, while the device is in the Inactive state with
no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not available on
all package types.
Frame Sync. The Frame Sync pulse is an 8 kHz signal that identifies Time Slot 0, Clock Slot
0 of a system’s PCM frame. The QLSLAC device references individual time slots with respect
to this input, which must be synchronized to PCLK.
Interrupt. INT is an active Low output signal which is programmable as either TTL compatible
or open drain. The INT output goes Low any time one of the input bits in the Real Time Data
register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed. INT remains Low until the appropriate register is read via
the microprocessor interface, or the QLSLAC device receives either a software or hardware
reset. The individual CDxy bits in the Real Time Data register can be masked from causing an
interrupt by using MPI Command 6C/6Dh. The transmit data interrupt must be armed with a
bit in the Operating Conditions register.
Master Clock (Input)/Enable CD1 Multiplex (Output). The Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the
internal clock is derived from the PCM Clock Input (PCLK), this pin can be used as an E1
output to control Legerity SLIC devices having multiplexed hookswitch and ground-key
detector outputs.
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or
out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum
clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual PCM
highway versions and 256 kHz for single PCM highway versions. The minimum clock rate
must be doubled if Linear state or PCM signaling is used. PCLK frequencies between 1.03
MHz and 1.53 MHz are not allowed. Optionally, the digital signal processor clock can be
derived from PCLK rather than MCLK.
Reset. A logic Low signal at this pin resets the QLSLAC device to its default state. The RST
pin may be tied to VCCD if it is not needed in the system.
Time Slot Control. The Time Slot Control outputs are open drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (High impedance). TSCA or TSCB is active
(Low) when PCM data is transmitted on the DXA or DXB pin respectively.
Analog and digital power supply inputs. VCCA and VCCD are provided to allow for noise
isolation and proper power supply decoupling techniques. For best performance, all of the
VCC power supply pins should be connected together at the connector of the printed circuit
board.
Analog Input. The analog voice band signal is applied to the VIN input of the QLSLAC device.
The VIN input is biased at VREF by a large internal resistor. The audio signal is sampled,
digitally processed and encoded, and then made available at the TTL-compatible PCM output
(DXA or DXB). If the digitizer saturates in the positive or negative direction, VIN is pulled by a
reduced resistance toward AGND or VCCD, respectively. VIN1 is the input for channel 1, VIN2
is the input for channel 2, VIN3 is the input for channel 3, and VIN4 is the input for channel 4.
Analog Output. The received digital data at DRA or DRB is processed and converted to an
analog signal at the VOUT pin. VOUT1 is the output from channel 1, VOUT2 is the output for
channel 2, VOUT3 is the output from channel 3, and VOUT4 is the output for channel 4. The
VOUT voltages are referenced to VREF.
Analog Voltage Reference. The VREF output is provided in order for an external capacitor to be
connected from VREF to ground, filtering noise present on the internal voltage reference.
VREF is buffered before it is used by internal circuitry. The voltage on VREF and the output
resistance are given in Electrical Characteristics, on page 13. The leakage current in the
capacitor must be low.
11
Zarlink Semiconductor Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet Le58QL031.PDF ] | |
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