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Teilenummer | Le58QL031DJC |
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Beschreibung | Quad Low Voltage Subscriber Line Audio-Processing Circuit | |
Hersteller | Legerity | |
Logo | ||
Gesamt 30 Seiten ™
Le58QL02/021/031
Quad Low Voltage Subscriber Line Audio-Processing Circuit
VE580 Series
APPLICATIONS
Codec function on telephone switch line cards
FEATURES
Low-power, 3.3 V CMOS technology with 5-V tolerant
digital inputs
Software and coefficient compatible to the Le79Q02/
021/031 QSLAC™ device
Performs the functions of four codec/filters
Software programmable:
— SLIC device input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock edge
options
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or
8.192 MHz master clock derived from MCLK or PCLK
Built-in test modes with loopback, tone generation,
and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Real Time Data register with interrupt (open drain or
TTL output)
Supports multiplexed SLIC device outputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
Maximum channel bandwidth for V.90 modems
RELATED LITERATURE
080754 Le58QL061/063 QLSLAC™ Device Data Sheet
080761 QSLAC™ to QLSLAC™ Device Design
Conversion Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
ORDERING INFORMATION
Device
Package (Green)1
Packing2
Le58QL02FJC
Le58QL021FJC
Le58QL021BVC
Le58QL031DJC
44-pin PLCC
44-pin PLCC
44-pin TQFP
32-pin PLCC
Tube
Tube
Tray
Tube
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2. For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
DESCRIPTION
The Le58QL02/021/031 Quad Low Voltage Subscriber Line
Audio-Processing Circuit (QLSLAC™) devices integrate the
key functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
Advanced submicron CMOS technology makes the Le58QL02/
021/031 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
Analog
VIN1
VOUT 1
VIN2
VOUT 2
VIN3
VOUT 3
VIN4
VOUT 4
VREF
SLIC
CD11
CD21
C31
C41
C51
CD12
CD22
C32
C42
C52
CD13
CD23
C33
C43
C53
CD14
CD24
C34
C44
C54
CHCLK
Signal Processing
Channel 1 (CH 1)
Signal Processing
Channel 2 (CH 2)
Signal Processing
Channel 3 (CH 3)
Signal Processing
Channel 4 (CH 4)
Clock
&
Reference
Circuits
Time Slot Assigner
(TSA)
SLIC
Interface
(SLI)
Dual/Single
PCM
Highway
DXA
DRA
TSCA
DXB
DRB
TSCB
FS
PCLK
MCLK/E1
Microprocessor Interface
(MPI)
INT CS DIO DCLK
Microprocessor
RST
Document ID# 080753 Date: May 24, 2006
Rev:
F Version: 1
Distribution: Public Document
CONNECTION DIAGRAMS
Figure 1. Le58QL02JC 44-Pin PLCC
VOUT 1
VIN1
VOUT 2
VIN2
VCCA
VREF
AGND
VIN3
VOUT 3
VIN4
VOUT 4
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
Le58QL02JC
12 34
13
44-Pin PLCC
33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
DCLK
DIO
TSCA
TSCB
DGND
PCLK
VCCD
DXA
DXB
FS
RST
6 Le58QL02/021/031 VE580 Series Data Sheet
6 Page ELECTRICAL CHARACTERISTICS
Typical values are for TA = 25º C and nominal supply voltages. Minimum and maximum values are over the temperature and
supply voltage ranges shown in Operating Ranges, except where noted.
Symbol
VIL
VIH
IIL
VHYS
VOL
VOH
IOL
GIN
VIR
VIOS
ZIN
IIP
IIN
ZOUT
CLOUT
IOUT
VREF
ZREF
VOR
VOOS
VOOSA
GAISN
PD
CI
CO
PSRR
Parameter Descriptions
Digital Input Low voltage
Digital Input High voltage
Digital Input leakage current
0 < V < VCCD
Otherwise
Digital Input hysteresis
Digital Output Low voltage
CD1–C5 (IOL = 4 mA)
CD1–C5 (IOL = 8 mA)
TSCA, TSCB (IOL =14 mA)
Other digital outputs (IOL = 2 mA)
Digital Output High voltage
CD1–C5 (IOH = 4 mA)
CD1–C5 (IOH = 8 mA)
Other digital outputs (IOH = 400 µA)
Digital Output leakage current (HI Z state)
0 < V < VCCD
Otherwise
Input attenuator gain
DGIN = 0
DGIN = 1
Analog input voltage range (Relative to VREF)
AX = 0 dB, attenuator on (DGIN = 0)
AX = 6.02 dB, attenuator on (DGIN = 0)
AX = 0 dB, attenuator off (DGIN = 1)
AX = 6.02 dB, attenuator off (DGIN = 1)
Offset voltage allowed on VIN
Analog input impedance to VREF, 300 to 3400 Hz
Current into analog input for an input voltage of 3.3 V
Current out of analog input for an input voltage of –0.3 V
VOUT output impedance
Allowable capacitance, VOUT to AGND
VOUT output current (F< 3400 Hz)
VREF output open circuit voltage (leakage < 20 nA)
VREF output impedance (F < 3400 Hz)
VOUT voltage range(AR = 0 dB)
(Relative to VREF)(AR = 6.02 dB)
VOUT offset voltage (AISN off)
VOUT offset voltage (AISN on)
AISN gain - expected gain (input = 0 dBm0, 1014 Hz)
Attenuator on (DGIN = 0)
Attenuator off (DGIN = 1)
Power dissipation
All channels active
1 channel active
All channels inactive
Digital Input capacitance
Digital Output capacitance
Power supply rejection ratio (1.02 kHz, 100 mVRMS, either
path, GX = GR = 0 dB)
Min
2.0
–7
–120
0.16
VCCD – 0.4 V
VCCD – 0.8 V
2.4
–7
–120
–50
600
50
50
–4
1.43
70
–40
–80
–0.016
–0.024
40
Typ
0.25
0.6438
1
±1.584
±0.792
±1.02
±0.51
1
1.5
±1.02
±0.51
130
40
13
Max Unit Note
0.8
V
+7
+180
0.34
0.4
0.8
0.4
0.4
µA
V
V
1
V1
+7
+180
µA
V/V
Vpk
50
1400
115
130
10
500
4
1.57
130
40
80
mV
kΩ
µA
Ω
pF
mApk
V
kΩ
Vpk
mV
0.016
0.024
V/V
170
80
mW
18
10
pF
10
dB
2
2
3
4
12 Le58QL02/021/031 VE580 Series Data Sheet
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ Le58QL031DJC Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
Le58QL031DJC | Quad Low Voltage Subscriber Line Audio-Processing Circuit | Legerity |
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