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A3PN010 Schematic ( PDF Datasheet ) - Microsemi Corporation

Teilenummer A3PN010
Beschreibung ProASIC3 nano Flash FPGAs
Hersteller Microsemi Corporation
Logo Microsemi Corporation Logo 




Gesamt 30 Seiten
A3PN010 Datasheet, Funktion
Revision 11
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® Designed to Secure FPGA Contents
Low Power
• Low Power ProASIC®3 nano Products
• 1.5 V Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rateand Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18 organization)
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
A3PN010 A3PN0151 A3PN020
A3PN060 A3PN125
ProASIC3 nano-Z Devices1
A3PN030Z1,2 A3PN060Z1 A3PN125Z1
System Gates
10,000
15,000 20,000
30,000
60,000
125,000
Typical Equivalent Macrocells
86 128 172
256
512 1,024
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)2
4,608-Bit Blocks2
260 384 520
768
1,536
3,072
– – – – 18 36
– ––
48
FlashROM Kbits
Secure (AES) ISP2
Integrated PLL in CCCs2
1 11
1
11
– – – – Yes Yes
– ––
11
VersaNet Globals
4 4 4 6 18 18
I/O Banks
2 33
2
22
Maximum User I/Os (packaged device)
34
49
49
77
71 71
Maximum User I/Os (Known Good Die)
34
– 52
83
71 71
Package Pins
QFN
VQFP
QN48
QN68
QN68 QN48, QN68
VQ100
VQ100
VQ100
Notes:
1. Not recommended for new designs.
2. A3PN030Z and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.
A3PN250
A3N250Z1
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
VQ100
† A3PN030 and smaller devices do not support this feature.
January 2013
© 2013 Microsemi Corporation
I






A3PN010 Datasheet, Funktion

6 Page









A3PN010 pdf, datenblatt
ProASIC3 nano Device Overview
SRAM and FIFO
ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along
their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have
independent read and write ports that can be configured with different bit widths on each port. For
example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM
blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro
(except in A3PN030 and smaller devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures
provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and
A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices
use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any
PLLs or programmable delays.
For devices using the six CCC block architecture, these six CCC blocks are located at the four corners
and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the
FPGA core or from dedicated connections to the CCC block, which are located near the CCC.
The CCC block has these key features:
• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis (for PLL only)
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
• Output duty cycle = 50% ± 1.5% or better (for PLL only)
• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
• Maximum acquisition time = 300 µs (for PLL only)
• Low power consumption of 5 mW
• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC) (for PLL only)
Global Clocking
ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
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