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ADuC7061 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADuC7061
Beschreibung Low Power Precision Analog Microcontroller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADuC7061 Datasheet, Funktion
Data Sheet
Low Power, Precision Analog Microcontroller,
Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI
ADuC7060/ADuC7061
FEATURES
Analog input/output
Dual (24-bit) ADCs
Single-ended and differential inputs
Programmable ADC output rate (4 Hz to 8 kHz)
Programmable digital filters
Built-in system calibration
Low power operation mode
Primary (24-bit) ADC channel
2 differential pairs or 4 single-ended channels
PGA (1 to 512) input stage
Selectable input range: ±2.34 mV to ±1.2 V
30 nV rms noise
Auxiliary (24-bit) ADC: 4 differential pairs or 7 single-
ended channels
On-chip precision reference (±10 ppm/°C)
Programmable sensor excitation current sources
200 μA to 2 mA current source range
Single 14-bit voltage output DAC
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
Multiple clocking options
Memory
32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel
4 kB (1 kB × 32) SRAM
Tools
In-circuit download, JTAG based debug
Low cost, QuickStart™ development system
Communications interfaces
SPI interface (5 Mbps)
4-byte receive and transmit FIFOs
UART serial I/O and I2C (master/slave)
On-chip peripherals
4× general-purpose (capture) timers including
Wake-up timer
Watchdog timer
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
16-bit, 6-channel PWM
General-purpose inputs/outputs
Up to 14 GPIO pins that are fully 3.3 V compliant
Power
AVDD/DVDD specified for 2.5 V (±5%)
Active mode: 2.74 mA (@ 640 kHz, ADC0 active)
10 mA (@ 10.24 MHz, both ADCs active)
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Packages and temperature range
Fully specified for −40°C to +125°C operation
32-lead LFCSP (5 mm × 5 mm)
48-lead LFCSP and LQFP
Derivatives
32-lead LFCSP (ADuC7061)
48-lead LQFP and 48-lead LFCSP (ADuC7060)
APPLICATIONS
Industrial automation and process control
Intelligent, precision sensing systems, 4 mA to 20 mA
loop-based smart sensors
GENERAL DESCRIPTION
The ADuC706x series are fully integrated, 8 kSPS, 24-bit data acqui-
sition systems incorporating high performance multichannel
sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 16-bit/
32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip.
The ADCs consist of a primary ADC with two differential pairs or
four single-ended channels and an auxiliary ADC with up to seven
channels. The ADCs operate in single-ended or differential input
mode. A single-channel buffered voltage output DAC is available
on chip. The DAC output range is programmable to one of four
voltage ranges.
The devices operate from an on-chip oscillator and a PLL gene-
rating an internal high frequency clock up to 10.24 MHz. The
microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine offering up to 10 MIPS peak performance; 4 kB of SRAM
and 32 kB of nonvolatile Flash/EE memory are provided on chip.
The ARM7TDMI core views all memory and registers as a single
linear array.
The ADuC706x contains four timers. Timer1 is a wake-up timer
with the ability to bring the part out of power saving mode. Timer2
is configurable as a watchdog timer. A 16-bit PWM with six output
channels is also provided. The ADuC706x contains an advanced
interrupt controller. The vectored interrupt controller (VIC) allows
every interrupt to be assigned a priority level. It also supports
nested interrupts to a maximum level of eight per IRQ and FIQ.
When IRQ and FIQ interrupt sources are combined, a total of 16
nested interrupt levels is supported. On-chip factory firmware
supports in-circuit serial download via the UART serial interface
ports and nonintrusive emulation via the JTAG interface. The parts
operate from 2.375 V to 2.625 V over an industrial temperature
range of −40°C to +125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009–2012 Analog Devices, Inc. All rights reserved.






ADuC7061 Datasheet, Funktion
ADuC7060/ADuC7061
Parameter
ADC SPECIFICATIONS: ANALOG
INPUT
Main Channel
Absolute Input Voltage Range
Input Voltage Range
(Differential Voltage
Between AIN+ and AIN–)
Common Mode Voltage, VCM10
Input Leakage Current1
Common-Mode Rejection DC1
On ADC Input
Common-Mode Rejection
50 Hz/60 Hz1
Normal-Mode Rejection
50 Hz/60 Hz1
On ADC Input
Auxiliary Channel
Absolute Input Voltage
Range1
Input Voltage Range
Common-Mode Rejection DC1
On ADC Input
Common-Mode Rejection
50 Hz/60 Hz1
Normal-Mode Rejection
50 Hz/60 Hz1
On ADC Input
VOLTAGE REFERENCE
ADC Precision Reference
Internal VREF
Initial Accuracy
Reference Temperature
Coefficient (Tempco)1, 11
Power Supply Rejection1
Test Conditions/Comments
Internal VREF = 1.2 V
Applies to both VIN+ and VIN−
Gain = 11
Gain = 21
Gain = 41
Gain = 81
Gain = 161
Gain = 321
Gain = 641
Gain = 1281
VCM = (AIN(+) + AIN(−))/2,
gain = 4 to 128
ADC0 and ADC1
ADC2, ADC3, ADC4, and ADC5
ADC6, ADC7, ADC8, and ADC9,
VREF+, VREF−
ADC = 7.8 mV
ADC = 1 V1
50 Hz/60 Hz ± 1 Hz, 16.6 Hz and
50 Hz update rate, chop on
ADC = 7.8 mV, range ± 20 mV
ADC = 1 V, range ± 1.2 V
50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC,
chop on
50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC,
chop off
Buffer enabled
Buffer disabled
Range-based reference source
ADC = 1 V1
50 Hz/60 Hz ± 1 Hz, 16.6 Hz and
50 Hz update rate, chop on
ADC = 1 V, range ± 1.2 V
50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC,
chop on
50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC,
chop off
Measured at TA = 25°C
Min
0.1
0
0
0
0
0
0
0
0
0.5
113
95
90
75
67
0.1
AGND
0
90
75
67
−0.1
−20
Rev. D | Page 6 of 108
Typ
10
15
15
95
87
1.2
±10
70
Data Sheet
Max Unit
VDD − 0.7
1.2
600
300
150
75
37.5
18.75
9.375
181
301
251
V
V
mV
mV
mV
mV
mV
mV
mV
V
nA
nA
nA
dB
dB
dB
dB
dB
dB
AVDD − 0.1
AVDD
1.2
V
V
V
dB
dB
dB
dB
V
+0.1 %
+20 ppm/°C
dB

6 Page









ADuC7061 pdf, datenblatt
ADuC7060/ADuC7061
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
tSH
tSL
tDOSU
tDAV
tDF
MSB
tDR
BITS 6 TO 1
tSR tSF
LSB
Data Sheet
MISO
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Table 5. SPI Slave Mode Timing (Phase Mode = 1)
Parameter Description
tCSE CSE to SCLOCK edge1
tSL SCLOCK low pulse width
tSH SCLOCK high pulse width
tDAV Data output valid after SCLOCK edge
tDSU Data input setup time before SCLOCK edge1
tDHD Data input hold time after SCLOCK edge1
tDF Data output fall time
tDR Data output rise time
tSR SCLOCK rise time
tSF SCLOCK fall time
tSFS CSE high after SCLOCK edge
Min
(2 × tHCLK) + (2 × tUCLK)
1 × tUCLK
2 × tUCLK
1
1
0
1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
30
30
Max Unit
ns
ns
ns
40 ns
ns
ns
40 ns
40 ns
ns
ns
ns
CS
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MISO
tCS
tSH
tDAV
tSL
tDF
MSB
tSR
tDR
BITS 6 TO 1
tSFS
tSF
LSB
MOSI
tDSU
MSB IN
BITS 6 TO 1
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
LSB IN
Rev. D | Page 12 of 108

12 Page





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