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AT45DB161E-MHD2B-T Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer AT45DB161E-MHD2B-T
Beschreibung 2.3V or 2.5V Minimum SPI Serial Flash Memory
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
AT45DB161E-MHD2B-T Datasheet, Funktion
Atmel AT45DB161E
16-Mbits DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports Atmel® RapidSoperation
Continuous Read capability through entire array
Up to 85MHz
Low-power Read option up to 10MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the Main Memory Array
Flexible programming options
Byte/Page program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible Erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Chip-scale BGA (5 x 5 x 1.2mm)
8782A–DFLASH–3/12






AT45DB161E-MHD2B-T Datasheet, Funktion
4. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated
opcodes are contained in Table 15-1 on page 40 through Table 15-4 on page 41. A valid instruction starts with the falling
edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the
CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address
location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit
(MSB) first.
Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using the terminology
BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. The main memory
addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes the 12 address
bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits required to designate a byte
address within the page.
For the "Power of 2" binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the
conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a
buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12 address
bits required to designate a page address, and A8 - A0 denotes the nine address bits required to designate a byte
address within a page.
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
6

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AT45DB161E-MHD2B-T pdf, datenblatt
The CS must be deasserted on a byte boundary (multiples of eight bits), otherwise the operation will be aborted and no
data will be programmed. The programming of the data bytes is internally self-timed and should take place in a maximum
time of tP (the program time will be a multiple of the tBP time depending on the number of bytes being programmed).
During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to erase or
program properly. If an erase programming error arises, it will be indicated by the EPE bit in the Status Register.
6.6 Page Erase
The Page Erase command can be used to individually erase any page in the Main Memory Array allowing the buffer to
Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer 1
command to be utilized at a later time.
To perform a Page Erase with the standard DataFlash page size (528 bytes), an opcode 81h must be clocked into the
device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the
page in the main memory to be erased, and 10 dummy bits.
To perform a Page Erase with the binary page size (512 bytes), an opcode 81h must be clocked into the device followed
by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main
memory to be erased, and nine dummy bits.
When a low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased state is a Logic 1).
The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the
RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to erase or
program properly. If an erase programming error arises, it will be indicated by the EPE bit in the Status Register.
6.7 Block Erase
A block of eight pages can be erased at one time. This command is useful when needing to pre-erase larger amounts of
memory and is more efficient than issuing eight separate Page Erase commands.
To perform a Block Erase with the standard DataFlash page size (528 bytes), an opcode 50h must be clocked into the
device followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 - PA3), and 13
dummy bits. The nine page address bits are used to specify which block of eight pages is to be erased.
To perform a Block Erase for the binary page size (512 bytes), an opcode 50h must be clocked into the device followed
by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and 12 dummy bits. The nine
page address bits are used to specify which block of eight pages is to be erased.
When a low-to-high transition occurs on the CS pin, the device will erase the selected block of eight pages. The erase
operation is internally self-timed and should take place in a maximum time of tBE. During this time, the RDY/BUSY bit in
the Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to erase or
program properly. If an erase programming error arises, it will be indicated by the EPE bit in the Status Register.
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
12

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