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AT45DB011D-SH-SL954 Schematic ( PDF Datasheet ) - Adesto

Teilenummer AT45DB011D-SH-SL954
Beschreibung 1-megabit 2.7-volt Minimum DataFlash
Hersteller Adesto
Logo Adesto Logo 




Gesamt 30 Seiten
AT45DB011D-SH-SL954 Datasheet, Funktion
Features
Single 2.7V to 3.6V Supply
RapidSSerial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 512-Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (32-Kbytes)
– Chip Erase (1Mbits)
One SRAM Data Buffer (256-/264-Bytes)
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25µA Standby Current Typical
– 15µA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1-megabit
2.7-volt
Minimum
DataFlash®
AT45DB011D
1. Description
The Adesto® AT45DB011D is a 2.7V, serial-interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB011D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 1,081,344-bits of memory are organized as 512 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB011D also contains one
SRAM buffer of 256-/264-bytes. EEPROM emulation (bit or byte alterability) is easily
handled with a self-contained three step read-modify-write operation. Unlike conven-
tional Flash memories that are accessed randomly with multiple address lines and a
parallel interface, the Adesto DataFlash® uses a RapidS serial interface to sequen-
tially access its data. The simple sequential access dramatically reduces active pin
count, facilitates hardware layout, increases system reliability, minimizes switching
noise, and reduces package size.
3639K–DFLASH–6/2014






AT45DB011D-SH-SL954 Datasheet, Funktion
(A16 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK
pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data
buffer and leaves the contents of the buffer unchanged.
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 264-bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first nine bits (PA8 - PA0) of the 18-bit address
sequence specify which page of the main memory array to read, and the last nine bits (BA8 -
BA0) of the 18-bit address sequence specify the starting byte address within the page. To per-
form a continuous read with the page size set to 256-bytes, the opcode, 03H, must be clocked
into the device followed by three address bytes (A16 - A0). Following the address bytes, addi-
tional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses the data buffer and
leaves the contents of the buffer unchanged.
6.4 Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 2,048 pages
in the main memory, bypassing the data buffer and leaving the contents of the buffer
unchanged. To start a page read from the DataFlash standard page size (264-bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and four don’t care bytes. The first nine bits (PA8 -
PA0) of the 18-bit address sequence specify the page in main memory to be read, and the last
nine bits (BA8 - BA0) of the 18-bit address sequence specify the starting byte address within
that page. To start a page read from the binary page size (256-bytes), the opcode D2H must be
clocked into the device followed by three address bytes and four don’t care bytes. The first nine
bits (A16 - A8) of the 17-bit sequence specify which page of the main memory array to read, and
the last eight bits (A7 - A0) of the 17-bit address sequence specify the starting byte address
within the page. The don’t care bytes that follow the address bytes are sent to initialize the read
6 AT45DB011D
3639K–DFLASH–6/2014

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AT45DB011D-SH-SL954 pdf, datenblatt
8.1.3
Figure 8-2. Disable Sector Protection
CS
SI
Opcode
Byte 1
Each transition
represents 8 bits
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Various Aspects About Software Controlled Protection
Software controlled protection is useful in applications in which the WP pin is not or cannot be
controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is
internally pulled high) and sector protection can be controlled using the Enable Sector Protection
and Disable Sector Protection commands.
If the device is power cycled, then the software controlled protection will be disabled. Once the
device is powered up, the Enable Sector Protection command should be reissued if sector pro-
tection is desired and if the WP pin is not used.
9. Hardware Controlled Protection
Sectors specified for protection in the Sector Protection Register and the Sector Protection Reg-
ister itself can be protected from program and erase operations by asserting the WP pin and
keeping the pin in its asserted state. The Sector Protection Register and any sector specified for
protection cannot be erased or reprogrammed as long as the WP pin is asserted. In order to
modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is perma-
nently connected to GND, then the content of the Sector Protection Register cannot be changed.
If the WP pin is deasserted, or permanently connected to VCC, then the content of the Sector
Protection Register can be modified.
The WP pin will override the software controlled protection method but only for protecting the
sectors. For example, if the sectors were not previously protected by the Enable Sector Protec-
tion command, then simply asserting the WP pin would enable the sector protection within the
maximum specified tWPE time. When the WP pin is deasserted; however, the sector protection
would no longer be enabled (after the maximum specified tWPD time) as long as the Enable Sec-
tor Protection command was not issued while the WP pin was asserted. If the Enable Sector
Protection command was issued before or while the WP pin was asserted, then simply deassert-
ing the WP pin would not disable the sector protection. In this case, the Disable Sector
Protection command would need to be issued while the WP pin is deasserted to disable the sec-
tor protection. The Disable Sector Protection command is also ignored whenever the WP pin is
asserted.
A noise filter is incorporated to help protect against spurious noise that may inadvertently assert
or deassert the WP pin.
The Table 9-1 details the sector protection status for various scenarios of the WP pin, the
Enable Sector Protection command, and the Disable Sector Protection command.
Figure 9-1. WP Pin and Protection Status
1
WP
23
12 AT45DB011D
3639K–DFLASH–6/2014

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