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AT25SF041 Schematic ( PDF Datasheet ) - Adesto

Teilenummer AT25SF041
Beschreibung 2.5V Minimum SPI Serial Flash Memory
Hersteller Adesto
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Gesamt 30 Seiten
AT25SF041 Datasheet, Funktion
AT25SF041
4-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support
Features
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm)
8-lead TSSOP (4 x 4 mm)
Die in Wafer Form
DS-25SF041–044F–4/2016






AT25SF041 Datasheet, Funktion
4. Device Operation
The AT25SF041 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25SF041 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF041
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 4-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
4.1 Dual Output Read
The AT25SF041 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of
data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
4.2 Quad Output Read
The AT25SF041 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer
of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO
pin.
5. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25SF041 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25SF041 memory array is 07FFFFh, address bits A23-A19 are always ignored by
the device.
AT25SF041
DS-25SF041–044F–4/2016
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AT25SF041 pdf, datenblatt
Figure 6-6. Quad-Output Read Array
CS
SCK
I/O0
(SI)
I/O1
(SO)
I/O2
(WP)
I/O3
(HOLD)
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Opcode
Address Bits A23-A0
Don't Care
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
OUT OUT OUT OUT OUT
0 1 1 0 1 0 1 1AAAAAA
06%
06%
High-impedance
A A A X X X X X X X X D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
06%
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
High-impedance
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
High-impedance
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
MSB MSB MSB MSB MSB
6.5 Quad-I/O Read Array(EBh)
The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. The Quad-I/O Read Array
command allows four bits of address to be clocked into the device on every clock cycle, rather than just one.
The Quad-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To
perform the Quad-I/O Read Array operation, the CS pin must first be asserted and then the opcode EBh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location
of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be
clocked into the device.
After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will
result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always
output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5,
and 4 of the same data byte will be output on the I/O2, I/O1 and I/O0 pins, respectively. During the next clock cycle, bits 3,
2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues
with each byte of data being output after every two clock cycles.
When the last byte (07FFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the I/O3, I/O2, I/O1 and I/O0 pins into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.The
Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array instruction.
AT25SF041
DS-25SF041–044F–4/2016
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