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AT25DF641A-SH-B Schematic ( PDF Datasheet ) - Adesto

Teilenummer AT25DF641A-SH-B
Beschreibung 2.7V Minimum SPI Serial Flash Memory
Hersteller Adesto
Logo Adesto Logo 




Gesamt 30 Seiten
AT25DF641A-SH-B Datasheet, Funktion
AT25DF641A
64-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual–I/O Support
Features
DATASHEET
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidSoperation
Supports Dual-Input Program and Dual-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output time (tV) of 5ns maximum
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
128 Sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte One-Time Programmable (OTP) Security Register
64 bytes factory preprogrammed
64 bytes user programmable
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast program and erase times
2.5ms typical Page Program (256 bytes) time
75ms typical 4KB Block Erase time
300ms typical 32KB Block Erase time
600ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
25mA Active Read current (typical at 20MHz)
5μA Deep Power-Down current (typical)
Endurance: 100,000 program/erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (0.208” wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
8793D–DFLASH–5/2013






AT25DF641A-SH-B Datasheet, Funktion
4. Memory Array
To provide the greatest flexibility, the AT25DF641A memory array can be erased in four levels of granularity including a
full Chip Erase. In addition, the array has been divided into physical sectors of uniform size, which can be individually
protected from program and erase operations. The size of the physical sectors is optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory
Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
Internal Sectoring for
Protection, Lockdown,
and Suspend Functions
64KB
(Sector 127)
64KB
(Sector 126)
64KB
Block Erase
(D8h Command)
32KB
Block Erase
(52h Command)
4KB
Block Erase
(20h Command)
Block Address
Range
64KB
32KB
32KB
64KB
32KB
32KB
4KB 7F F F F F h – 7F F 000h
4KB 7F E F F F h – 7F E 000h
4KB 7F DF F F h – 7F D000h
4KB 7F CF F F h – 7F C000h
4KB 7F BF F F h – 7F B000h
4KB 7F AF F F h – 7F A000h
4KB 7F 9F F F h – 7F 9000h
4KB 7F 8F F F h – 7F 8000h
4KB 7F 7F F F h – 7F 7000h
4KB 7F 6F F F h – 7F 6000h
4KB 7F 5F F F h – 7F 5000h
4KB 7F 4F F F h – 7F 4000h
4KB 7F 3F F F h – 7F 3000h
4KB 7F 2F F F h – 7F 2000h
4KB 7F 1F F F h – 7F 1000h
4KB 7F 0F F F h – 7F 0000h
4KB 7E F F F F h – 7E F 000h
4KB 7E E F F F h– 7E E 000h
4KB 7E DF F F h – 7E D000h
4KB 7E CF F F h – 7E C000h
4KB 7E BF F F h – 7E B000h
4KB 7E AF F F h – 7E A000h
4KB 7E 9F F F h – 7E 9000h
4KB 7E 8F F F h – 7E 8000h
4KB 7E 7F F F h – 7E 7000h
4KB 7E 6F F F h – 7E 6000h
4KB 7E 5F F F h – 7E 5000h
4KB 7E 4F F F h – 7E 4000h
4KB 7E 3F F F h – 7E 3000h
4KB 7E 2F F F h – 7E 2000h
4KB 7E 1F F F h – 7E 1000h
4KB 7E 0F F F h – 7E 0000h
64KB
(Sector 0)
64KB
32KB
32KB
4KB 00F F F F h – 00F 000h
4KB 00E F F F h – 00E 000h
4KB 00DF F F h – 00D000h
4KB 00CF F F h – 00C000h
4KB 00BF F F h – 00B000h
4KB 00AF F F h – 00A000h
4KB 009F F F h – 009000h
4KB 008F F F h – 008000h
4KB 007F F F h – 007000h
4KB 006F F F h – 006000h
4KB 005F F F h – 005000h
4KB 004F F F h – 004000h
4KB 003F F F h – 003000h
4KB 002F F F h – 002000h
4KB 001F F F h – 001000h
4KB 000F F F h – 000000h
Page Program Detail
1-256 byte
Page Program
(02h Command)
Page Address
Range
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
7FFFFFh– 7FFF00h
7FFEFFh– 7FFE00h
7F F DF F h – 7F F D00h
7FFCFFh – 7FFC00h
7FFBFFh – 7FFB00h
7F F AF F h – 7F F A00h
7FF9FFh – 7FF900h
7FF8FFh – 7FF800h
7FF7FFh – 7FF700h
7FF6FFh – 7FF600h
7FF5FFh – 7FF500h
7FF4FFh – 7FF400h
7FF3FFh – 7FF300h
7FF2FFh – 7FF200h
7FF1FFh – 7FF100h
7FF0FFh – 7FF000h
7FEFFFh– 7FEF00h
7FEEFFh– 7FEE00h
7F E DF F h – 7F E D00h
7FECFFh– 7FEC00h
7FEBFFh– 7FEB00h
7F E AF F h – 7F E A00h
7FE9FFh – 7FE900h
7FE8FFh – 7FE800h
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
0017FFh – 001700h
0016FFh – 001600h
0015FFh – 001500h
0014FFh – 001400h
0013FFh – 001300h
0012FFh – 001200h
0011FFh – 001100h
0010FFh – 001000h
000FFFh – 000F00h
000EFFh – 000E00h
000DF F h – 000D00h
000CFFh – 000C00h
000BFFh – 000B00h
000AF F h – 000A00h
0009FFh – 000900h
0008FFh – 000800h
0007FFh – 000700h
0006FFh – 000600h
0005FFh – 000500h
0004FFh – 000400h
0003FFh – 000300h
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
6

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AT25DF641A-SH-B pdf, datenblatt
8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed
into previously erased memory locations. An erased memory location is one that has all eight bits set to the Logical 1
state (a byte value of FFh). Before a Byte/page Program command can be started, the Write Enable command must
have been previously issued to the device (see “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the
Status Register to a Logical 1 state.
Note:
The internal programming operation of the AT25DF641A occurs on a nibble-wide basis, and all four bits of
the nibble must be in an erased state (Logic 1 state) prior to the programming of any of the four bits. If any
one of the four bits is in the programmed state (Logic 0 state) and an attempt is made to program one of the
other four bits in the nibble from a Logic 1 to a Logic 0, then the contents of the nibble cannot be guaranteed
and may contain erroneous data.
Example 1: A 4KB Block Erase is performed to erase the first 4KB block of memory (all bytes set to FFh). The
application then programs the first byte location with a value of 7Fh (0111 1111). Without erasing the 4KB
block again, the application then attempts to program the same byte location with BFh (1011 1111)
expecting that the resulting byte value stored in memory will be 3Fh (0011 1111). However, because of the
way the AT25DF641A programs bytes internally and because all four bits of the most-significant nibble were
not in the erased state prior to the programming of the BFh value, the most-significant nibble will not contain
the value of 0011b but will instead contain a different value.
Example 2: A 4KB Block Erase is performed to erase the first 4KB block of memory (all bytes set to FFh). The
application then programs the first byte location with a value of 7Fh (0111 1111). Without erasing the 4KB
block again, the application then attempts to program the same byte location with FCh (1111 1100),
expecting that the resulting byte value stored in memory will be 7Ch (0111 1100). The resulting byte value
stored in the memory will indeed be 7Ch because no additional bits in the most-significant nibble were being
programmed from a Logic 1 to a Logic 0, and all four bits in the least-significant nibble were in the erased
state prior to the programming of the 7Ch byte value.
To perform a Byte/Page Program command, a 02h opcode must be clocked into the device followed by the three address
bytes denoting the first location of the memory array to begin programming at. After the address bytes have been clocked
in, data can then be clocked into the device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not
all 0), then special circumstances regarding which memory locations are to be programmed will apply. In this situation,
any data that is sent to the device that goes beyond the end of the page will wrap around to the beginning of the same
page. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched
into the internal buffer.
Example:
If the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh, while the last byte of
data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h
through 0000FDh) will not be programmed and will remain in the erased state (FFh).
When the CS pin is deasserted, the device will take the data stored in the internal buffer into the appropriate memory
array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If
less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and
will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in
a time of tPP or tBP if only programming a single byte.
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
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