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AT25DF081A Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer AT25DF081A
Beschreibung 8-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 53 Seiten
AT25DF081A Datasheet, Funktion
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 16 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
Fast Program and Erase Times
– 1.0ms Typical Page Program (256 Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
8-Mbit
2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory
Atmel AT25DF081A
Preliminary
8715B–SFLSH–8/10






AT25DF081A Datasheet, Funktion
5. Device Operation
The Atmel® AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly
referred to as the SPI Master. The SPI Master communicates with the AT25DF081A via the SPI bus which is com-
prised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF081A features a dual-input program mode in which the SO pin becomes an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Pro-
gram command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-
Output Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect
to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The
AT25DF081A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes
0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and
not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and
always output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruc-
tion dependent information such as address and data bytes would then be clocked out by the host controller. All
opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by
deasserting the CS pin.
Opcodes not supported by the AT25DF081A will be ignored by the device and no operation will be started. The
device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being
deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address
information is sent to the device, then no operation will be performed and the device will simply return to the idle
state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DF081A memory array is 0FFFFFh, address bits A23-A20 are always
ignored by the device.
6 Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10

6 Page









AT25DF081A pdf, datenblatt
Figure 8-1. Byte Program
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN
0 0 0 0 0 0 1 0AAAAAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
Figure 8-2. Page Program
CS
SCK
SI
SO
0123456789
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
0 0 0 0 0 0 1 0AAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
DATA IN BYTE n
DDDDDDDD
MSB
12 Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10

12 Page





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