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CD4027BCN Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer CD4027BCN
Beschreibung Dual J-K Master/Slave Flip-Flop
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 6 Seiten
CD4027BCN Datasheet, Funktion
October 1987
Revised January 1999
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to VDD and VSS.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s Low power: 50 nW (typ.)
s Medium speed operation: 12 MHz (typ.) with 10V
supply
Ordering Code:
Order Number Package Number
Package Description
CD4027BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4027BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Top View
Inputs tn1
(Note 1)
Outputs tn
(Note 2)
CL J K S R Q Q
Q
(Note 3)
 I XOOO I
O
 XOOO I I
O
 OXOOO O
I
 X I OO I O
I
 XXOOX
(No Change)
X XX I OX I
O
X XXO I X O
I
X XX I I X I
I
I = HIGH Level
O = LOW Level
X = Don't Care
 = LOW-to-HIGH
 = HIGH-to-LOW
Note 1: tn1 refers to the time interval prior to the positive clock pulse
transition
Note 2: tn refers to the time intervals after the positive clock pulse
transition
Note 3: Level Change
© 1999 Fairchild Semiconductor Corporation DS005958.prf
www.fairchildsemi.com






CD4027BCN Datasheet, Funktion
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assumeany responsibility for use of any circuitry described, no circuit patent licenses are impliedandFairchildreserves theright at any timewithout noticetochange saidcircuitry andspecifications.

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