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HCPL-0701 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer HCPL-0701
Beschreibung LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 11 Seiten
HCPL-0701 Datasheet, Funktion
LOW INPUT CURRENT
HIGH GAIN SPLIT
DARLINGTON OPTOCOUPLERS
HCPL-0700
HCPL-0701
DESCRIPTION
The HCPL-0700 and HCPL-0701 optocouplers consist of an AlGaAs LED optically coupled to a high gain split darlington
photodetector housed in a compact 8-pin small outline package.
The split darlington configuration separating the input photodiode and the first stage gain from the output transistor permits lower
output saturation voltage and higher speed operation than possible with conventional darlington phototransistor optocoupler.
The combination of a very low input current of 0.5 mA and a high current transfer ratio of 2000% makes this family particularly
useful for input interface to MOS, CMOS, LSTTL and EIA RS232C, while output compatibility is ensured to CMOS as well as high
fan-out TTL requirements.
FEATURES
• Low current - 0.5 mA
• Superior CTR-2000%
• Superior CMR-10 kV/µs
• CTR guaranteed 0-70°C
• *BSI, CSA and UL approval
PACKAGE DIMENSIONS
0.164 (4.16)
0.144 (3.66)
APPLICATIONS
• Digital logic ground isolation
• Telephone ring detector
• EIA-RS-232C line receiver
• High common mode noise
line receiver
• µP bus isolation
• Current loop receiver
N/C 1
+2
V
F
_3
N/C 4
8
V
CC
7
V
B
6V
O
5 GND
HCPL-0700 / HCPL-0701
Pin 1
0.202 (5.13)
0.182 (4.63)
0.143 (3.63)
0.123 (3.13)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
NOTE
All dimensions are in inches (millimeters)
© 2003 Fairchild Semiconductor Corporation
Page 1 of 11
8/18/03






HCPL-0701 Datasheet, Funktion
HCPL-0700
LOW INPUT CURRENT
HIGH GAIN SPLIT
DARLINGTON OPTOCOUPLERS
HCPL-0701
TYPICAL PERFORMANCE CURVES
Fig. 4 Propagation Delay vs. Temperature
35
VCC = 5 V
30 IF = 0.5 mA
RL = 4.7 k
1/f = 50 µs
25
tPLH
20
15
10
5
0
-60 -40 -20
0
20 40 60
TA - TEMPERATURE (˚C)
tPHL
80 100
Fig. 6 Propagation Delay vs. Temperature
4
IF = 12 mA
VCC = 5 V
RL = 270
1/f = 50 µs
3
tPLH
2
1
0
-60 -40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
tPHL
80 100
Fig. 5 Propagation Delay vs. Temperature
20
18
IF = 1.6 mA
16
VCC = 5 V
RL = 2.2 k
14 1/f = 50 µs
tPLH
12
10
8
6
4
tPHL
2
0
-60 -40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
80 100
Fig. 7 Logic High Output Current vs. Temperature
1000 VCC = VO = 5.5 V
100
10
1
0.1
0.01
-40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
80 100
© 2003 Fairchild Semiconductor Corporation
Page 6 of 11
8/18/03

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