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HN27C256AG Schematic ( PDF Datasheet ) - Hitachi Semiconductor

Teilenummer HN27C256AG
Beschreibung 32768-word x 8-bit UV Erasable and Programmable ROM
Hersteller Hitachi Semiconductor
Logo Hitachi Semiconductor Logo 




Gesamt 16 Seiten
HN27C256AG Datasheet, Funktion
HN27C256AG Series
32768-word × 8-bit UV Erasable and Programmable ROM
Maintenance only
Description
This Hitachi HN27C256AG is a 256-kbit ultraviolet erasable and electrically programmable ROM, featuring
high speed and low power dissipation. Fabricated on advanced fine process and high speed circuitry
technique, the HN27C256AG makes high speed access time possible for 16 bit microprocessors such as the
8086 and 68000. And low power dissipation in active and standby modes matches our CMOS 256-kbit
EPROM. In programming operation, the HN27C256AG realizes faster programming times than our
conventional 256-kbit EPROM by Hitachi’s Fast High-Reliability Programming Algorithm. Pin arrangement,
pin configuration and programming voltage are compatible with our 256-kbit EPROM series, therefore
existing programmers can be used with the HN27C256AG.
Features
High speed
Access time: 100/120/150 ns (max)
Low power dissipation
Active mode: 25 mW (typ) (f = 1 MHz)
Standby mode: 5 µW (typ)
High reliability and fast programming
Programming voltage: +12.5 V DC
Fast High-Reliability Programming Algorithm available
Device identifier mode
Manufacturer code and device code
Ordering Information
Type No.
HN27C256AG-10
HN27C256AG-12
HN27C256AG-15
Access Time
100 ns
120 ns
150 ns
Package
600-mil 28-pin cerdip (DG-28)
Note: This device is not available for new application.






HN27C256AG Datasheet, Funktion
HN27C256AG Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VPP = VCC)
Test Conditions
Input pulse levels: 0.45 V to 2.4 V
Input rise and fall time: 10 ns
Output load: 1TTL gate + 100 pF
Reference levels for measuring timing: Inputs; 0.8 V and 2.0 V
Outputs; 0.8 V and 2.0 V
HN27C256AG
-10 -12 -15
Parameter
Symbol Min Max Min Max Min Max Unit Test Conditions
Address to output delay tACC
— 100 — 120 — 150 ns CE = OE = VIL
CE to output delay
t CE
— 100 — 120 — 150 ns OE = VIL
OE to output delay
t OE
— 60 — 60 — 70 ns CE = VIL
OE high to output float tDF
0 35 0 40 0 50 ns CE = VIL
Address to output hold tOH
5 — 5 — 5 — ns CE = OE = VIL
Note: tDF is defined as the time at which the output achieves the open circuit condition and data is no longer
driven.
Read Timing Waveform
Address
CE Standby Mode
OE
Data Out
Active Mode
tCE
Standby Mode
tACC
tOE
tDF
tOH
Data Out Valid

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HN27C256AG pdf, datenblatt
HN27C256AG Series
DC Characteristics (Ta = 25°C ± 5°C, VCC = 6 V ± 0.25 V, VPP = 12.5 V ± 0.5 V)
Parameter
Symbol Min Typ Max Unit Test Conditions
Input leakage current
ILI — — 2
µA Vin = 0 V to VCC
VPP supply current
IPP — — 30 mA CE = VIL
Operating VCC current
ICC — — 30 mA
Input low level
VIL
–0.1*5
0.8
V
Input high level
VIH 2.2 —
VCC + 0.5*6 V
Output low voltage during verify VOL
0.45 V
IOL = 2.1 mA
Output high voltage during verify VOH 2.4 —
V
IOH = –400 µA
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. VPP must not exceed 13.5 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.
5V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V or 12.5 V to VIL when CE = Low.
5. VIL min = –0.6 V for pulse width 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.

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SeitenGesamt 16 Seiten
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