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PDF L6227 Data sheet ( Hoja de datos )

Número de pieza L6227
Descripción DMOS dual full bridge driver
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! L6227 Hoja de datos, Descripción, Manual

L6227
DMOS dual full bridge driver with PWM current controller
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Datasheet - production data
Features
Operating supply voltage from 8 to 52 V
2.8 A output peak current (1.4 A DC)
RDS(ON) 0.73 typ. value at Tj = 25 °C
Operating frequency up to 100 KHz
Non-dissipative overcurrent protection
Dual independent constant tOFF PWM current
controllers
Slow decay synchronous rectification
Cross conduction protection
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Applications
Bipolar stepper motor
Dual DC motor
Description
The L6227 device is a DMOS dual full bridge
designed for motor control applications, realized
in BCD technology, which combines isolated
DMOS power transistors with CMOS and bipolar
circuits on the same chip. The device also
includes two independent constant off time PWM
current controllers that performs the chopping
regulation. Available in PowerDIP24 (20 + 2 + 2),
PowerSO36 and SO24 (20 + 2 + 2) packages, the
L6227 device features a non-dissipative
overcurrent protection on the high-side Power
MOSFETs and thermal shutdown.
February 2014
This is information on a product in full production.
DocID9453 Rev 2
1/32
www.st.com

1 page




L6227 pdf
L6227
Maximum ratings
Table 3. Thermal data
Symbol
Description
PowerDIP24 SO24 PowerSO36 Unit
Rth-j-pins Maximum thermal resistance junction pins
19 15
-
Rth-j-case
Rth-j-amb1
Rth-j-amb1
Rth-j-amb1
Rth-j-amb2
Maximum thermal resistance junction case
Maximum thermal resistance junction ambient(1)
Maximum thermal resistance junction ambient(2)
Maximum thermal resistance junction ambient(3)
Maximum thermal resistance junction ambient(4)
- -2
44 52
-
- - 36
- - 16
59 78 63
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness
of 35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness
of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness
of 35 µm), 16 via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heat sinking surface on the board.
C/W
C/W
C/W
C/W
C/W
C/W
DocID9453 Rev 2
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L6227 arduino
L6227
5 Circuit description
Circuit description
5.1
Power stages and charge pump
The L6227 device integrates two independent power MOS full bridges. Each power MOS
has an RDS(ON) = 0.73 (typical value at 25 °C), with intrinsic fast freewheeling diode.
Cross conduction protection is achieved using a deadtime (td = 1 s typical) between the
switch off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.
Table 6. Charge pump external components values
Component
Value
CBOOT
CP
RP
D1
D2
220 nF
10 nF
100
1N4148
1N4148
Figure 5. Charge pump circuit
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5.2 Logic inputs
Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS compatible logic inputs. The internal
structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds are
respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins ENA and ENB have identical input structure with the exception that the drains of the
overcurrent and thermal protection MOSFETs (one for the bridge A and one for the
bridge B) are also connected to these pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB inputs may be driven in one of two
configurations as shown in Figure 7 or 8. If driven by an open drain (collector) structure,
DocID9453 Rev 2
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