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AX24C64A Schematic ( PDF Datasheet ) - AXElite

Teilenummer AX24C64A
Beschreibung 32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Hersteller AXElite
Logo AXElite Logo 




Gesamt 14 Seiten
AX24C64A Datasheet, Funktion
AX24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
General Description
The AX24C32A/AX24C64A provides 32,768/65,536
bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as
4096/8192 words of 8 bits each. The device is
optimized for use in many industrial and commercial
applications where low-power and low-voltage
operation are essential. The AX24C32A/AX24C64A
is available in space-saving SOP-8, TSSOP-8 and
DFN-8 (only AX24C32A) packages and is accessed
via a two-wire serial interface.
Features
Wide Voltage Operation
- VCC = 1.8V to 5.5V
Operating Ambient Temperature:
-40°C to +85°C
Internally Organized:
- AX24C32A, 4096 X 8 (32K bits)
- AX24C64A, 8192 X 8 (64K bits)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V)
Compatibility
Write Protect Pin for Hardware Data Protection
32-byte Page (32K, 64K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
SOP-8, TSSOP-8 and DFN-8 packages
Pin Configuration
SOP-8
TSSOP-8
DFN-8
Pin Configuration
Pin Name
A0 - A2
SDA
SCL
WP
GND
VCC
Functions
AWdrdirtesPsrIontpeuctts
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
Axelite Confidential Materials, do not copy or distribute without written consent.
1/14
Rev.1.1 Jul.22, 2011






AX24C64A Datasheet, Funktion
AX24C32A/64A
Device Addressing
The 32K, and 64K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see to Figure 4).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits must
compare to their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will
return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5).
PAGE WRITE: The 32K/64K EEPROM is capable of an 32-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 31 (32K/64K) more data words. The EEPROM will respond with a "0" after
each data word received. The microcontroller must terminate the page write sequence with a stop condition
(see Figure 6).
The data word address lower five (32K/64K) bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location. When
the word address, internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than 32 (32K/64K) data and previous data will be overwritten. words are
transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.
6/14
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.1 Jul.22, 2011

6 Page









AX24C64A pdf, datenblatt
AX24C32A/64A
Mechanical Dimensions
OUTLINE DRAWING SOP 8
Available package typesAX24C32A/64A
Top View
End View
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
b
C
D
E1
E
e
L
θ
MIN MAX
1.35 1.75
0.10 0.25
0.31 0.51
0.17 0.25
4.70 5.10
3.80 4.00
5.79 6.20
1.27 BSC
0.40 1.27
0° 8°
Axelite Confidential Materials, do not copy or distribute without written consent.
12/14
Rev.1.1 Jul.22, 2011

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