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AD9776 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9776
Beschreibung Digital-to-Analog Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9776 Datasheet, Funktion
Dual 12-/14-/16-Bit,
1 GSPS, Digital-to-Analog Converters
AD9776/AD9778/AD9779
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range, digital-to-analog converters (DACs) that pro-
vide a sample rate of 1 GSPS, permitting multicarrier generation
up to the Nyquist frequency. They include features optimized
for direct conversion transmit applications, including complex
digital modulation, and gain and offset compensation. The DAC
outputs are optimized to interface seamlessly with analog quad-
rature modulators such as the AD8349. A serial peripheral interface
(SPI®) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over a
range of 10 mA to 30 mA. The devices are manufactured on an
advanced 0.18 μm CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in 100-lead TQFP packages.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable set up and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
COMPLEX I AND Q
DC
FPGA/ASIC/DSP
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DIGITAL INTERPOLATION FILTERS
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
AD9779
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.






AD9776 Datasheet, Funktion
AD9776/AD9778/AD9779
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter
Conditions
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
Maximum Input Data Rate at Interpolation
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High
Output VOUT Logic Low
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
SYNC_I+ = VIA, SYNC_I− = VIB
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN2
LVDS Input Rate
Set-Up Time, SYNC_I to DAC Clock
Hold Time, SYNC_I to DAC Clock
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, RO
Single-ended
Maximum Clock Rate
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage (CLK+, CLK−)3
Common-Mode Voltage
Maximum Clock Rate4
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Min Typ Max Unit
2.0 V
0.8 V
300 MSPS
250 MSPS
200 MSPS
125 MSPS
2.4 V
0.4 V
825
−100
80
20
−0.2
1
1575
+100
120
125
mV
mV
mV
Ω
MSPS
ns
ns
825 1575 mV
1025
mV
150 200 250 mV
1150
1250 mV
80 100 120 Ω
1 GHz
400 800 2000 mV
300 400 500 mV
1 GSPS
40 MHz
12.5 ns
12.5 ns
1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
2 Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.
3 When using the PLL, a differential swing of 2 V p-p is recommended.
4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.
Rev. A | Page 6 of 56

6 Page









AD9776 pdf, datenblatt
AD9776/AD9778/AD9779
Pin
No. Mnemonic
41 P2D<12>
42 P2D<11>
43 DVDD18
44 DGND
45 P2D<10>
46 P2D<9>
47 P2D<8>
48 P2D<7>
49 P2D<6>
50 P2D<5>
51 P2D<4>
52 P2D<3>
53 DVDD18
54 DGND
55 P2D<2>
56 P2D<1>
57 P2D<0>
58 NC
59 NC
60 DVDD18
61 DVDD33
62 SYNC_O−
63 SYNC_O+
64 DGND
65 PLL_LOCK
66 SDO
67 SDIO
68 SCLK
69 CSB
70 RESET
71 IRQ
72 AGND
73 IPTAT
Description
Port 2, Data Input D12.
Port 2, Data Input D11.
1.8 V Digital Supply.
Digital Common.
Port 2, Data Input D10.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input D7.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
1.8 V Digital Supply.
Digital Common.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D0 (LSB).
No Connect.
No Connect.
1.8 V Digital Supply.
3.3 V Digital Supply.
Differential Synchronization Output.
Differential Synchronization Output.
Digital Common.
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Analog Common.
Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 10 μA at 25°C with
approximately 20 nA/°C slope. This
pin should remain floating.
Pin
No. Mnemonic
74 VREF
75 I120
76 AVDD33
77 AGND
78 AVDD33
79 AGND
80 AVDD33
81 AGND
82 AGND
83 OUT2_P
84 OUT2_N
85 AGND
86 AUX2_P
87 AUX2_N
88 AGND
89 AUX1_N
90 AUX1_P
91 AGND
92 OUT1_N
93 OUT1_P
94 AGND
95 AGND
96 AVDD33
97 AGND
98 AVDD33
99 AGND
100 AVDD33
Description
Voltage Reference Output.
120 μA Reference Current.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
Analog Common.
Differential DAC Current Output,
Channel 2.
Differential DAC Current Output,
Channel 2.
Analog Common.
Auxiliary DAC Current Output,
Channel 2.
Auxiliary DAC Current Output,
Channel 2.
Analog Common.
Auxiliary DAC Current Output,
Channel 1.
Auxiliary DAC Current Output,
Channel 1.
Analog Common.
Differential DAC Current Output,
Channel 1.
Differential DAC Current Output,
Channel 1.
Analog Common.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
Rev. A | Page 12 of 56

12 Page





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