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CY7C037-20AC Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY7C037-20AC
Beschreibung Dual-Port Static RAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 19 Seiten
CY7C037-20AC Datasheet, Funktion
25/0251
CY7C027/028
CY7C037/038
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 32K x 16 organization (CY7C027)
• 64K x 16 organization (CY7C028)
• 32K x 18 organization (CY7C037)
• 64K x 18 organization (CY7C038)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
Active: ICC = 180 mA (typical)
Standby: ISB3 = 0.05 mA (typical)
Logic Block Diagram
R/WL
UBL
32K/64K x 16/18
Dual-Port Static RAM
Fully asynchronous operation
Automatic power-down
Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Separate upper-byte and lower-byte control
Dual Chip Enables
Pin select for Master or Slave
Commercial and industrial temperature ranges
Available in 100-pin TQFP
Pin-compatible and functionally equivalent to IDT7027
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
[2]
I/O8/9LI/O15/17L
[3]
I/O0LI/O7/8L
8/9
8/9
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8/9 [2]
I/O8/9LI/O15/17R
8/9 [3]
I/O0LI/O7/8R
[4]
A0LA14/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
[4]
A0RA14/15R
[4]
A0LA14/15L
15/16
15/16
[4]
A0RA14/15R
CEL Interrupt CER
OEL Semaphore
OER
R/WL
SEML
BUSYL[5]
INTL
UBL
LBL
Arbitration
M/S
R/WR
SEMR
[5]
BUSYR
INTR
UBR
LBR
Notes:
1. See page 6 for Load Conditions.
2. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices.
3. I/O0I/O7 for x16 devices; I/O0I/O8 for x18 devices.
4. A0A14 for 32K; A0A15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06042 Rev. *A
Revised December 27, 2002






CY7C037-20AC Datasheet, Funktion
CY7C027/028
CY7C037/038
Capacitance[12]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
C = 30 pF
R1 = 893
R2 = 347
OUTPUT
RTH = 250
C = 30 pF
OUTPUT
VTH = 1.4V
C = 5 pF
5V
R1 = 893
R2 = 347
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
ALL INPUT PULSES
3.0V
GND
10%
3 ns
90%
90%
10%
3 ns
AC Test Loads (Applicable to -12 only)[13]
1.00
OUTPUT
Z0 = 50R = 50
C
0.90
0.80
0.70
(a) Load 1 (-12 only)
VTH = 1.4V
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0
5 10 15 20 25 30
Capacitance (pF)
(b) Load Derating Curve
Notes:
12. Tested initially and after any design or process changes that may affect these parameters.
13. Test Conditions: C = 0 pF.
Document #: 38-06042 Rev. *A
Page 6 of 19

6 Page









CY7C037-20AC pdf, datenblatt
CY7C027/028
CY7C037/038
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[41]
ADDRESSR
R/WR
tWC
MATCH
tPWE
DATA INR
ADDRESSL
BUSYL
DATAOUTL
tPS
MATCH
tBLA
tSD
VALID
tHD
tDDD
tBHA
tBDD
tWDD
VALID
Write Timing with Busy Input (M/S=LOW)
R/W
BUSY
tWB
tPWE
tWH
Note:
41. CEL = CER = LOW.
Document #: 38-06042 Rev. *A
Page 12 of 19

12 Page





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