CY7C027-20AXI Datasheet PDF - Cypress Semiconductor
| Part Number | CY7C027-20AXI | |
| Description | 32K / 64K x 16 Dual-Port Static RAM | |
| Manufacturers | Cypress Semiconductor | |
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CY7C02732 K / 64 K × 16 Dual-Port Static RAM
CY7C027
CY7C028
32 K / 64 K × 16 Dual-Port Static RAM
32 K / 64 K × 16 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 32 K × 16 organization (CY7C027)
■ 64 K × 16 organization (CY7C028)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15 and 20 ns
■ Low operating power
■ Active: ICC = 180 mA (typical)
■ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power down
Logic Block Diagram
R/WL
UBL
■ Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and industrial temperature ranges
■ Available in 100-pin TQFP
■ Pb-free packages available
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
I/O8L–I/O15[1L]
I/O0L–I/O[72L]
8
8
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8 I/O8L–I/[O1]15R
8 I/O0L–I/O[2]7R
A0L–A[134]/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
A0R–A[134] /15R
A0L–A[134]/15L
CEL
OEL
R/WL
SEML
BUSYL[4]
INTL
UBL
LBL
15/16
Notes
1. I/O8–I/O15 for × 16 devices
2. I/O0–I/O7 for × 16 devices
3. A0–A14 for 32K; A0–A15 for 64K devices.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
15/16
A0R–A[134] /15R
CER
OER
R/WR
SEMR
[4] BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06042 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 28, 2013
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CY7C027
CY7C028
Selection Guide
Parameter
Maximum Access Time
Typical Operating Current
Typical Standby Current for ISB1 (Both ports TTL level)
Typical Standby Current for ISB3 (Both ports CMOS level)
CY7C027/CY7C028
-15
15
190
50
0.05
CY7C027/CY7C028
-20
20
180
45
0.05
Unit
ns
mA
mA
mA
Pin Definitions
Left Port
CE0L, CE1L
R/WL
OEL
A0L–A15L
I/O0L–I/O15L
SEML
UBL
LBL
INTL
BUSYL
M/S
VCC
GND
NC
Right Port
CE0R, CE1R
R/WR
OER
A0R–A15R
I/O0R–I/O15R
SEMR
UBR
LBR
INTR
BUSYR
Description
Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
Read/Write Enable
Output Enable
Address (A0–A14 for 32K; A0–A15 for 64K devices)
Data Bus Input/Output (I/O0–I/O15 for × 16 devices)
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for × 16 devices)
Lower Byte Select (I/O0–I/O7 for × 16 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
Document Number: 38-06042 Rev. *J
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CY7C027-20AXI electronic component. |
| Information | Total 23 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CY7C027-20AXI.PDF Datasheet ] | |
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