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CY7C028 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY7C028
Beschreibung 32K / 64K x 16 Dual-Port Static RAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 23 Seiten
CY7C028 Datasheet, Funktion
CY7C02732 K / 64 K × 16 Dual-Port Static RAM
CY7C027
CY7C028
32 K / 64 K × 16 Dual-Port Static RAM
32 K / 64 K × 16 Dual-Port Static RAM
Features
True dual-ported memory cells which allow simultaneous
access of the same memory location
32 K × 16 organization (CY7C027)
64 K × 16 organization (CY7C028)
0.35 micron CMOS for optimum speed and power
High speed access: 15 and 20 ns
Low operating power
Active: ICC = 180 mA (typical)
Standby: ISB3 = 0.05 mA (typical)
Fully asynchronous operation
Automatic power down
Logic Block Diagram
R/WL
UBL
Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
Pin select for Master or Slave
Commercial and industrial temperature ranges
Available in 100-pin TQFP
Pb-free packages available
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
I/O8L–I/O15[1L]
I/O0L–I/O[72L]
8
8
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8 I/O8L–I/[O1]15R
8 I/O0L–I/O[2]7R
A0L–A[134]/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
A0R–A[134] /15R
A0L–A[134]/15L
CEL
OEL
R/WL
SEML
BUSYL[4]
INTL
UBL
LBL
15/16
Notes
1. I/O8–I/O15 for × 16 devices
2. I/O0–I/O7 for × 16 devices
3. A0–A14 for 32K; A0–A15 for 64K devices.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
15/16
A0R–A[134] /15R
CER
OER
R/WR
SEMR
[4] BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06042 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 28, 2013






CY7C028 Datasheet, Funktion
CY7C027
CY7C028
Maximum Ratings
Exceeding maximum ratings [6] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.3 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State ...................................... –0.5 V to +7.0 V DC
Input Voltage [7] ...........................................–0.5 V to +7.0 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 1100V
Latch-Up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
–40 °C to +85 °C
VCC
5 V 10%
5 V 10%
Electrical Characteristics
Over the Operating Range
Symbol
Parameter
VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA)
VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA)
VIH Input HIGH Voltage
VIL Input LOW Voltage
IOZ Output Leakage Current
ICC Operating Current
(VCC = Max, IOUT= 0 mA)
Outputs Disabled
Commercial
Industrial
ISB1 Standby Current
(Both Ports TTL Level)
CEL & CER VIH, f = fMAX
Commercial
Industrial
ISB2 Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Commercial
Industrial
ISB3 Standby Current
Commercial
(Both Ports CMOS Level)
CEL & CER VCC – 0.2 V, f = 0
Industrial
ISB4 Standby Current
Commercial
(One Port CMOS Level)
CEL | CER VIH, f = fMAX[8]
Industrial
Min
2.4
2.2
–10
CY7C027/CY7C028
-15
Typ Max Min
– – 2.4
0.4 –
– 2.2
0.8 –
10 –10
190 280
-20
Typ
180
305
50 70
45
60
120 180
110
125
0.05 0.5
0.05
0.05
110 160
100
115
Unit
Max
–V
0.4 V
–V
0.8 V
10 A
265 mA
290 mA
65 mA
80 mA
160 mA
175 mA
0.5 mA
0.5 mA
140 mA
155 mA
Notes
6. The voltage on any input or I/O pin cannot exceed the power pin during power up.
7. Pulse width < 20 ns.
8. fIMSBA3X. = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
Document Number: 38-06042 Rev. *J
Page 6 of 23

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CY7C028 pdf, datenblatt
CY7C027
CY7C028
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side [34]
A0–A 2
SEM
VALID ADRESS
tAW
tSCE
tHA
tSAA
VALID ADRESS
tSOP
tACE
tOHA
I/O0
R/W
OE
tSD
DATAIN VALID
tSA
tPWE
tHD
DATAOUT VALID
WRITE CYCLE
tSWRD
tSOP
tDOE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention [35, 36, 37]
A0L –A2L
MATCH
R/WL
SEM L
A 0R–A2R
R/WR
SEM R
tSPS
MATCH
Notes
34. CE = HIGH for the duration of the above timing (both write and read cycle).
35. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
36. Semaphores are reset (available to both ports) at cycle start.
37. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document Number: 38-06042 Rev. *J
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