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6N137M Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 6N137M
Beschreibung Single-Channel High-Speed 10 MBit/s Logic Gate Optocouplers
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 18 Seiten
6N137M Datasheet, Funktion
April 2013
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
High-Speed 10 MBit/s Logic Gate Optocouplers
Features
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/µs
Fan-out of 8 Over -40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR-open Collector
U.L. Recognized (File # E90700, Vol. 2)
Applications
Ground Loop Elimination
LSTTL to TTL, LSTTL or 5 V CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer-peripheral Interface
Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common
mode rejection of typically 10 kV/µs. The HCPL2601M
and HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Schematics
Package Outlines
N/C 1
+2
V
F
_3
N/C 4
8
V
CC
7V
E
+1
V
F1
_2
6V
O
5 GND
_3
V
F2
+4
8
V
CC
7V
01
6V
02
5 GND
6N137M
HCPL2601M
HCPL2611M
HCPL2630M
HCPL2631M
(Preliminary)
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
Figure 1. Schematics
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
8
1
8
1
8
8
1
1
Figure 2. Package Options
Truth Table (Positive Logic)
Input
Enable
HH
LH
HL
LL
H NC
L NC
Output
L
H
H
H
L
H
www.fairchildsemi.com






6N137M Datasheet, Funktion
Typical Performance Curves
For Single-Channel Devices: 6N137M, HCPL2601M, and HCPL2611M
0.8
IF = 5 mA
0.7 VE = 2 V
VCC = 5.5 V
0.6
0.5
0.4
0.3
IOL = 9.6 mA
0.2
0.1
IOL = 12.8 mA
IOL = 16 mA
IOL = 6.4 mA
10
1
0.100
0.010
0.0
-40
-20 0 20 40 60
TA – AMBIENT TEMPERATURE (°C)
80
100
Figure 3. Low Level Output Voltage vs. Ambient Temperature
0.001
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
VF – FORWARD VOLTAGE (V)
Figure 4. Input Diode Forward Voltage vs. Forward Current
120
VCC = 5 V
TA = 25°C
100
80 RL = 4 kΩ (tPLH)
60 RL = 350 Ω (tPLH)
RL = 1 kΩ (tPLH)
40
RL = 4 kΩ (tPHL)
20 RL = 1 kΩ (tPHL)
RL = 350 Ω (tPHL)
0
5 7 9 11 13 15
IF – FORWARD CURRENT (mA)
Figure 5. Switching Time vs. Forward Current
50
45
40
35
30
VCC = 5 V
25
VE = 2 V
VOL = 0.6 V
IF = 15 mA
IF = 10 mA
IF = 5 mA
20
-40
-20 0 20 40 60
TA – AMBIENT TEMPERATURE (°C)
80
100
Figure 6. Low Level Output vs. Ambient Temperature
4.0
VCC = 5 V
3.5 VE = 2 V
VOL = 0.6 V
3.0
2.5
2.0
1.5
RL = 350 Ω
RL = 1 kΩ
RL = 4 kΩ
1.0
-40
-20 0 20 40 60
TA – AMBIENT TEMPERATURE (°C)
80
100
Figure 7. Input Threshold Current vs. Ambient Temperature
6
5
4
RL = 1 kΩ
3
RL = 350 Ω
2
RL = 4 kΩ
1
0
012345
IF - FORWARD CURRENT (mA)
Figure 8. Output Voltage vs. Input Forward Current
6
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
6
www.fairchildsemi.com

6 Page









6N137M pdf, datenblatt
Package Dimensions
Through Hole
43
56
21
78
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
0.200 (5.08)
MAX
0.022 (0.56)
0.016 (0.41)
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68)
0.020 (0.51)
MIN
0.154 (3.90)
0.120 (3.05)
0.100 (2.54) TYP
0.016 (0.40)
0.008 (0.20)
15° MAX
0.300 (7.62)
TYP
0.4" Lead Spacing (Option TV) (Pending)
43
21
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
56
78
0.200 (5.08)
MAX
0.022 (0.56)
0.016 (0.41)
0.031 (0.78)
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68)
0.020 (0.51)
MIN
0.154 (3.90)
0.120 (3.05)
0.100 (2.54) TYP
0.016 (0.40)
0.008 (0.20)
0° to 15°
0.400 (10.16)
TYP
Surface Mount – 0.3" Lead Spacing (Option S)
0.390 (9.91)
0.370 (9.40)
4 32 1
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
8-Pin Surface Mount DIP – Land Pattern
(Option S)
0.070 (1.78)
0.060 (1.52)
5 67 8
0.156 (3.94)
0.144 (3.68)
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.020 (0.51)
MIN
0.016 (0.40)
0.008 (0.20)
0.295 (7.49)
0.415 (10.54)
0.100 (2.54)
0.030 (0.76)
0.200 (5.08)
MAX
0.022 (0.56)
0.016 (0.41)
0.015 (0.40) MIN
Both Sides
0.100 (2.54)
TYP
0.315 (8.00)
MIN
0.405 (10.30)
MAX.
Note:
All dimensions are in inches (millimeters)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
12
www.fairchildsemi.com

12 Page





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