|
|
Teilenummer | CY7C4281V |
|
Beschreibung | Low-Voltage Deep Sync FIFOs | |
Hersteller | Cypress Semiconductor | |
Logo | ||
Gesamt 22 Seiten CY7C4261V
CY7C4281V/CY7C4291V
16K/64K/128K × 9
Low-Voltage Deep Sync™ FIFOs
16K/64K/128K × 9 Low-Voltage Deep Sync™ FIFOs
Features
■ 3.3 V operation for low-power consumption and easy
integration into low-voltage systems
■ High-speed, low-power, first-in first-out (FIFO) memories
■ 16K × 9 (CY7C4261V)
■ 64K × 9 (CY7C4281V)
■ 128K × 9 (CY7C4291V)
■ 0.35-micron CMOS for optimum speed or power
■ High-speed 100-MHz operation (10-ns read/write cycle times)
■ Low power
❐ ICC = 25 mA
❐ ISB = 4 mA
■ Fully asynchronous and simultaneous read and write operation
■ Empty, full, and programmable Almost Empty and Almost Full
status flags
■ Output-enable (OE) pin
■ Independent read- and write-enable pins
■ Supports free-running 50% duty cycle clock inputs
■ Width-expansion capability
■ Pin-compatible 3.3 V solutions for CY7C4261/81/91
■ Pin-compatible density upgrade within the CY7C42X1V family
■ Pb-free packages available
Functional Description
The CY7C4261/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine bits
wide. The CY7C4261/81/91V are pin-compatible with the lower
densities in the CY7C42x1V Synchronous FIFO family.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
Selection Guide
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1
and WEN2/LD are held active, data is continually written into the
FIFO on each WCLK cycle. The output port is controlled in a
similar manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the
CY7C4261/81/91V has an output-enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run
independently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion is
possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow of
data.
The CY7C4261/81/91V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to single
word granularity. The programmable flags default to Empty +7
and Full –7.
The flags are synchronous, that is, they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full, and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using an advanced 0.35 μ
CMOS technology. Input ESD protection is greater than 2001 V,
and latch-up is prevented by the use of guard rings.
For a complete list of related documentation, click here.
Description
Maximum frequency
Maximum access time
Minimum cycle time
Minimum data or enable setup
Minimum data or enable hold
Maximum flag delay
Active power supply current (ICC1)
Commercial
7C4261/81V-10
100
8
10
3.5
0
8
25
7C4261/91V-15
66.7
10
15
4
0
10
25
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4261V
16K × 9
32-pin PLCC
CY7C4281V
64K × 9
32-pin PLCC
CY7C4291V
128K × 9
32-pin PLCC
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06013 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2016
CY7C4261V
CY7C4281V/CY7C4291V
and write operation. The next time WEN2/LD is brought LOW, a
write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register contents
to the data outputs. Writes and reads should not be performed
simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in Table 1 or the default values are used, the programmable
almost-empty flag (PAE) and programmable almost-full flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
Table 1. Writing the Offset Registers [1]
LD WEN WCLK
Selection
00
Empty offset (LSB)
Empty offset (MSB)
Full offset (LSB)
Full offset (MSB)
01
No operation
Table 1. Writing the Offset Registers (continued) [1]
LD WEN WCLK
Selection
10
Write into FIFO
11
No operation
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is referred
to as n and determines the operation of PAE. PAE is synchronized to
the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW
when the FIFO contains n or fewer unread words. PAE is set
HIGH by the LOW-to-HIGH transition of RCLK when the FIFO
contains (n+1) or greater unread words.
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF. PAF is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4261V (16k – m), CY7C4281V (64k – m) and
CY7C4291V (128k – m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.
Table 2. Status Flags
CY7C4261V
0
1 to n[2]
(n + 1) to (16384 − (m + 1))
(16384 − m)[3] to 16383
16384
Number of Words in FIFO
CY7C4281V
0
1 to n[2]
(n + 1) to (65536 − (m + 1))
(65536 − m)[3] to 65535
65536
CY7C4291V
0
1 to n[2]
(n + 1) to (131072 − (m + 1))
(131072 − m)[3] to 131071
131072
FF PAF PAE EF
HHL L
HH L H
HHHH
H L HH
L LHH
Notes
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document Number: 38-06013 Rev. *K
Page 6 of 22
6 Page CY7C4261V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
Figure 8. Reset Timing [14]
RS
REN1,
REN2
tRS
tRSS
tRSS
tRSR
tRSR
WEN1
WEN2/LD [16]
EF,PAE
FF, PAF
Q0 − Q8
tRSS
tRSF
tRSF
tRSF
tRSR
OE = 1[15]
OE=0
Notes
14. The clocks (RCLK, WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Document Number: 38-06013 Rev. *K
Page 12 of 22
12 Page | ||
Seiten | Gesamt 22 Seiten | |
PDF Download | [ CY7C4281V Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
CY7C4281-10JC | 64K/128K x 9 Deep Sync FIFOs | Cypress Semiconductor |
CY7C4281-10JI | 64K/128K x 9 Deep Sync FIFOs | Cypress Semiconductor |
CY7C4281-15JC | 64K/128K x 9 Deep Sync FIFOs | Cypress Semiconductor |
CY7C4281-25JC | 64K/128K x 9 Deep Sync FIFOs | Cypress Semiconductor |
CY7C4281V | Low-Voltage Deep Sync FIFOs | Cypress Semiconductor |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |