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Am29LV200BT-120FIB Schematic ( PDF Datasheet ) - Advanced Micro Devices

Teilenummer Am29LV200BT-120FIB
Beschreibung 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
Hersteller Advanced Micro Devices
Logo Advanced Micro Devices Logo 




Gesamt 30 Seiten
Am29LV200BT-120FIB Datasheet, Funktion
Am29LV200B
Data Sheet
The Am29LV200B is not offered for new designs. Please contact a Spansion representative for alter-
nates.
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro and
changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21521 Revision D Amendment 6 Issue Date October 10, 2006
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Am29LV200BT-120FIB Datasheet, Funktion
DATA SHEET
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Regulated Voltage Range: VCC = 3.0–3.6 V
Full Voltage Range: VCC = 2.7–3.6 V
Max access time, ns (tACC)
Max CE# access time, ns (tCE)
Max OE# access time, ns (tOE)
Note: See “AC Characteristics” for full specifications.
55R
55
55
30
BLOCK DIAGRAM
RY/BY#
VCC
VSS
RESET#
Sector Switches
Erase Voltage
Generator
Am29LV200B
70 90
70 90
70 90
30 35
120
120
120
50
DQ0DQ15 (A-1)
Input/Output
Buffers
WE#
BYTE#
CE#
OE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
STB Latch
VCC Detector
A0–A16
Timer
Y-Decoder
STB
X-Decoder
Y-Gating
Cell Matrix
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21521D6 October 10, 2006

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Am29LV200BT-120FIB pdf, datenblatt
DATA SHEET
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Am29LV200B Command
Definitions” section has details on erasing a sector or
the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC Char-
acteristics table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RESET#
pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write com-
mands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array
data. The operation that was interrupted should be rein-
itiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3 V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3 V, the standby current will be
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
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21521D6 October 10, 2006

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