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H9CKNNN8GTMPLR-NUH Schematic ( PDF Datasheet ) - Hynix

Teilenummer H9CKNNN8GTMPLR-NUH
Beschreibung 8Gb LPDDR3
Hersteller Hynix
Logo Hynix Logo 




Gesamt 70 Seiten
H9CKNNN8GTMPLR-NUH Datasheet, Funktion
168ball FBGA Specification
8Gb LPDDR3 (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.1 / Oct. 2013
1






H9CKNNN8GTMPLR-NUH Datasheet, Funktion
Ball ASSIGNMENT
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A ADNU DNU NC
NC
NC
NC
NC
NC
NC
NC
VDD1
VSSQ
DQ30
DQ29
VSSQ
DQ26
DQ25
VSSQ
DQS3_
c
VDD1
VSS
DNU
DNU
B BDNU DNU VDD1 NC
NC
NC
NC
NC
NC
VSS
VDD2 DQ31 VDDQ DQ28
DQ27
VDDQ
DQ24
DQS3_
t
VDDQ
DM3
VDD2
DNU
DNU
C VSS VDD2
DQ15 VSSQ
C
D NC NC
VDDQ DQ14
D
E NC NC
DQ12 DQ13
E
F NC NC
DQ11 VSSQ
F
G NC NC
VDDQ DQ10
G
H NC NC
DQ8 DQ9
H
J NC NC
K NC NC
L NC NC
Top View
DQS1_
t
VSSQ
VDDQ
DQS1_
c
VDD2 DM1
J
K
L
M NC VSS
VREF
(DQ)
VSS
M
N NC VDD1
P
ZQ
VREF
(CA)
R VSS VDD2
168ball 12x12 PoP
x32 LPDDR3 only
VDD1 DM0
DQS0_
c
VSSQ
VDDQ
DQS0_
t
N
P
R
T CA9 CA8
DQ6 DQ7
T
U CA7 VDDCA
DQ5 VSSQ
U
V VSSCA CA6
VDDQ DQ4
V
W CA5 VDDCA
DQ2 DQ3
W
Y CK_c CK_t
DQ1 VSSQ
Y
AA VSS VDD2
VDDQ DQ0 AA
AB
AC
DNU DNU CS0
NC VDD1 CA1 VSSCA CA3
CA4
VDD2
VSS
DQ16 VDDQ DQ18
DQ20
VDDQ
DQ22
DQS2_
t
VDDQ
DM2
VDD2
DNU
DNU
DNU DNU CKE0 NC
VSS CA0 CA2 VDDCA NC
NC
NC
VSSQ
DQ17
DQ19
VSSQ
DQ21
DQ23
VSSQ
DQS2_
c
VDD1
VSS
DNU DNU
AB
AC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
LPDDR3 Commend / Address
Power (LPDDR3 : VDD1,VDD2,VDDCA,VREF)
LPDDR3 Data IO
Ground (LPDDR3 : VSS,VSSCA,VSSQ)
Rev 1.1 / Oct. 2013
6

6 Page









H9CKNNN8GTMPLR-NUH pdf, datenblatt
STATE DIAGRAM
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
Power
Applied
Resetting
MR
Reading
Resetting
Power
Down
PR, PRA
Power
On
DPDX
MRR
RESET
Resetting
PD
PDX
RESET
MR
Writing
MRW
MRR
Idle
MR
Reading
Deep
Power
Down
DPD
SREF
Self
Refreshing
SREFX
Idle1
ACT
PD
PDX
REF
Idle
Power
Down
Active
Power
Down
PDX
PD
Write
WR
Active*1
MRR
Active
MR
Reading
RD
RD
Refreshing
Automatic Sequence
Command Sequence
Writing
WRA
WRA
Reading
RDA
RDA
Writing
with
Autoprecharge
PR, PRA
Reading
with
Autoprecharge
Precharging
PR(A) = Precharge (All)
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
RESET = Reset is achieved through MRW command
MRW = Mode Register Write
MRR = Mode Register Read
PD = Enter Power Down
PDX = Exit Power Down
SREF = Enter Self Refresh
SREFX = Exit Self Refresh
DPD = Enter Deep Power Down
DPDX = Exit Deep Power Down
REF = Refresh
Rev 1.1 / Oct. 2013
12

12 Page





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