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PDF SST26VF016B Data sheet ( Hoja de datos )
| Número de pieza | SST26VF016B | |
| Descripción | 3.0V 16 Mbit Serial Quad I/O (SQI) Flash Memory | |
| Fabricantes | Microchip | |
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SST26VF016B / SST26VF016BA
3.0V 16 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 104 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 μA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay blocks
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed
identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-lead SOIJ (208mil)
- 8-lead SOIC (150 mil)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF016B/016BA also
support full command-set compatibility to traditional
Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board
space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
The SST26VF016B/016BA significantly improve per-
formance and reliability , while lowering power con-
sumption. These devices write (Program or Erase) with
a single power supply of 2.7-3.6V . The total energy
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is
less than alternative flash memory technologies.
SST26VF016B/016BA are offered in 8-contact WDFN
(6 mm x 5 mm), 8-lead SOIJ (208 mil), and 8-lead
SOIC (150 mil). See Figures 2-1 through 2-3 for pin
assignments.
Two configurations are available upon order:
SST26VF016B default at power-up has the WP# and
Hold# pins enabled and SST26VF016BA default at
power-up has the WP# and Hold# pins disabled.
2014 Microchip Technology Inc.
Advance Information
DS20005262A-page 1
http://www.Datasheet4U.com
1 page  
3.0 MEMORY ORGANIZATION
The SST26VF016B/016BA SQI memory array is orga-
nized in uniform, 4 KByte erasable sectors with the fol-
lowing erasable blocks: eight 8 KByte parameter, two
32 KByte overlay , and thirty 64 KByte overlay blocks.
See Figure 3-1.
FIGURE 3-1:
MEMORY MAP
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
SST26VF016B / SST26VF016BA
64 KByte
64 KByte
64 KByte
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
4 KByte
4 KByte
4 KByte
4 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block
20005262 F41.0
2014 Microchip Technology Inc.
Advance Information
DS20005262A-page 5
5 Page 
SST26VF016B / SST26VF016BA
4.6.1 I/O CONFIGURATION (IOC)
The I/O Configuration (IOC) bit re-configures the I/O
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the
Configuration register. When IOC bit is ‘0’ the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3
pin are enabled (SPI Quad I/O Configuration setup).
The IOC bit must be set to ‘1’ before issuing the follow-
ing SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), and SPI Quad page program (32H).
Without setting the IOC bit to ‘1’, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up for
SST26VF016B is ‘0’ and for SST26VF016BA is ‘1’.
4.6.2
BLOCK-PROTECTION VOLATILITY
STATE (BPNV)
The Block-Protection V olatility State bit indicates
whether any block has been permanently locked with
the non-V olatile W rite-Lock Lock-Down register
(nVWLDR). When no bits in the nVWLDR have been
set, the BPNV is ‘1’; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to ‘1’, the BPNV bit will be ‘0’ from that point forward,
even after power-up.
4.6.3 WRITE-PROTECT ENABLE (WPEN)
The Write-Protect Enable (WPEN) bit is a non-volatile
bit that enables the WP# pin.
The W rite-Protect (WP#) pin and the W rite-Protect
Enable (WPEN) bit control the programmable hard-
ware write-protect feature. Setting the WP# pin to low,
and the WPEN bit to ‘1’, enables Hardware write-pro-
tection. To disable Hardware write protection, set either
the WP# pin to high or the WPEN bit to ‘0’. There is
latency associated with writing to the WPEN bit. Poll
the BUSY bit in the Status register , or wait TWPEN, for
the completion of the internal, self-timed W rite opera-
tion. When the chip is hardware write protected, only
Write operations to Block-Protection and Configuration
registers are disabled. See “Hardware W rite Protec-
tion” on page 7 and Table 4-1 on page 7 for more infor-
mation about the functionality of the WPEN bit.
2014 Microchip Technology Inc.
Advance Information
DS20005262A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST26VF016B.PDF ] | |
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