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PDF MT4HTF1664HY Data sheet ( Hoja de datos )
| Número de pieza | MT4HTF1664HY | |
| Descripción | DDR2 SDRAM SODIMM | |
| Fabricantes | Micron Technology | |
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128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMM
Features
DDR2 SDRAM SODIMM
MT4HTF1664HY – 128MB
MT4HTF3264HY – 256MB
MT4HTF6464HY – 512MB
Features
• 200-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), or
512MB (64 Meg x 64)
• VDD = VDDQ = 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent opera-
tion
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1: 200-Pin SODIMM (MO-224 R/C C)
Module height: 30mm (1.18in)
Options
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)1
• Package
– 200-pin DIMM (lead-free)
• Frequency/CL2
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)3
– 5.0ns @ CL = 3 (DDR2-400)3
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
800
–
–
–
Data Rate (MT/s)
CL = 5
CL = 4
800 533
667 533
667 553
– 553
– 400
CL = 3
400
400
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
12.5
15
15
15
15
tRC
(ns)
55
55
55
55
55
PDF: 09005aef8161d160
htf4c16_32_64x64h.pdf - Rev. I 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
SDA
RDQSx,
RDQS#x
Err_Out#
VDD/VDDQ
VDDSPD
VREF
VSS
NC
NF
NU
RFU
Type
I/O
Output
Output
(open drain)
Supply
Supply
Supply
Supply
–
–
–
–
Description
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Parity error output: Parity error found on the command and address bus.
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
SPD EEPROM power supply: 1.7–3.6V.
Reference voltage: VDD/2.
Ground.
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functionality.
Not used: These pins are not used in specific module configurations/operations.
Reserved for future use.
PDF: 09005aef8161d160
htf4c16_32_64x64h.pdf - Rev. I 3/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.
5 Page 
128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
Parameter
-80E/-
Symbol 800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
540 480 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD1
IDD2P
660 600 540 520 mA
28 28 28 28 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); IDD2Q 260 260 220 180 mA
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2N 280 280 240 200 mA
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
IDD3P
160 140 120 100 mA
48 48 48 48
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
IDD3N 300 280 240 200 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
IDD4W 1180 1000 820 640 mA
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst IDD4R 1100 940 780 620 mA
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
920 740 700 680 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 28 28 28 28 mA
PDF: 09005aef8161d160
htf4c16_32_64x64h.pdf - Rev. I 3/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.
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