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ISL6366 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL6366
Beschreibung Dual 6-Phase + 1-Phase PWM Controller
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 44 Seiten
ISL6366 Datasheet, Funktion
Dual 6-Phase + 1-Phase PWM Controller for VR12/IMVP7
Applications
ISL6366
The ISL6366 is a dual PWM controller; its 6-phase PWMs control
the microprocessor core or memory voltage regulator, while its
single-phase PWM controls the peripheral voltage regulator for
graphics, system agent, or processor I/O.
The ISL6366 utilizes Intersil’s proprietary Enhanced Active Pulse
Positioning (EAPP) modulation scheme to achieve the extremely
fast transient response with fewer output capacitors.
The ISL6366 is designed to be compliant to Intel VR12/IMVP7
specifications. It accurately monitors the load current via the
IMON pin and reports this information via the IOUT register to
the microprocessor, which sends a PSI# signal to the controller
at low power mode via SVID bus. The controller enters 1- or
2-phase operation in low power mode (PSI1); in the ultra low
power mode (PSI2,3), it can further drop the number of phases
and enable the diode emulation ofthe operational phase.In low
power modes, the magnetic core and switching losses are
significantly reduced, yielding high efficiency at light load. After
the PSI# signal is de-asserted, the dropped phase(s) are added
back to sustain heavy load transient response and efficiency.
Today’s microprocessors require a tightly regulated output voltage
position versus load current (droop). The ISL6366 senses the
output current continuously by measuring thevoltage acrossthe
dedicated current sense resistor or the DCRof the output
inductor. The sensed current flows outof the FB pinto develop the
precision voltage drop across the feedback resistor for droop
control. Currentsensing circuitsalso provide the needed signals
for channel-currentbalancing, average overcurrent protection and
individual phase current limiting. TheTM and TMS pins are to
sense anNTC thermistor’s temperature, which is internally
digitizedfor thermal monitoring and for integrated thermal
compensation of the current sense elements of therespective
regulator.
The ISL6366 features remote voltage sensing and completely
eliminates any potential difference between remote and local
grounds. This improves regulation and protection accuracy. The
threshold-sensitive enable input is available to accurately
coordinate the start-up of the ISL6366 with other voltage rails.
Features
• Intel VR12/IMVP7 Compliant
- SerialVID with Programmable IMAX, TMAX, BOOT,
ADDRESS OFFSET Registers
• Intersil’s Proprietary Enhanced Active Pulse Positioning
(EAPP) Modulation Scheme, Patented
- Voltage Feed-forward and Ramp Adjustable Options
- High Frequency and PSI Compensation Options
- Variable Frequency Control During Load Transients to
Reduce Beat Frequency Oscillation
- Linear Control with Evenly Distributed PWM Pulses for
Better Phase Current Balance During Load Transients
•D ual Outputs
- Output 1 (VR0): 1 to 6-Phase, Coupled Inductor
Compatibility, for Core or Memory
- Output 2 (VR1): Single Phase for Graphics, System Agent,
or Processor I/O
- Differential Remote Voltage Sensing
- ±0.5% Closed-loop System Accuracy Over Load, Line and
Temperature
- Phase Doubler Compatibility (NOT Phase Dropping)
• Proprietary Active Phase Adding and Dropping with Diode
Emulation Scheme For Enhanced Light Load Efficiency
• Programmable Slew Rate of Fast Dynamic VID with
Dynamic VID Compensation (DVC) for VR0
• Dynamic VID Compensation (DVS) for VR1 at No Droop
• Droop and Diode Emulation Options
• Programmable 1 or 2-Phase Operation in PSI1/2/3 Mode
• Programmable Standard or Coupled-Inductor Operation
• Precision Resistor or DCR Differential Current Sensing
- Integrated Programmable Current Sense Resistors
- Integrated Thermal Compensation
- Accurate Load-Line (Droop) Programming
- Accurate Channel-Current Balancing
- Accurate Current Monitoring
• Average Overcurrent Protection and Channel Current Limit
With Internal Current Comparators
• Precision Overcurrent Protection on IMON & IMONS Pins
• Independent Oscillators, up to 1MHz Per Phase, for Cost,
Efficiency, and Performance Optimization
• Dual Thermal Monitoring and Thermal Compensation
• Start-up Into Pre-Charged Load
• Pb-Free (RoHS Compliant)
Janu ar y 3, 20 11
FN6964.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL6366 Datasheet, Funktion
ISL6366
Typical Application: 6-Phase Coupled-Inductor VR and 1-Phase VR
+5V
VTT
SVDATA
SVALERT#
SVCLK
VR_RDY
VR_RDYS
VR_HOT#
OVP
DVC FB
PSICOMP
HFCOMP
COMP VCC PWM1
ISEN1-
ISEN1+
VSEN
RGND
EN_VTT
PWM4
ISEN4-
ISEN4+
ISL6366
VIN
VIN
EN_PWR
RAMP_ADJ
IMON
IMONS
FS_DRP
FSS_DRPS
+5V
+5V
+5V
BTS_DES_TCOMPS
BT_FDVID_TCOMP
GND
+5V
+5V
ADDR_IMAXS_TMAX
NPSI_DE_IMAX
PWMS
ISENS-
ISENS+
+5V TMS
NTC
NTC
TM
SICI
RGNDS
VSENS
HFCOMPS/DVCS
RSET COMPS FBS
+5V
NTC: BETA = 3477
+5V
VCC
PWM
BOOT
ISL6627
DRIVER
UGATE
PHASE
GND
LGATE
+5V
VCC
PWM
BOOT
ISL6627
DRIVER
UGATE
PHASE
GND
LGATE
VIN
VIN
PWM2/5
ISEN2/5-
ISEN2/5+
PWM3/6
ISEN3/6-
ISEN3/6+
VIN
+5V
VCC
PWM
BOOT
ISL6627
DRIVER
UGATE
PHASE
GND
LGATE
NTC1 NETWORK IS NOT NEEDED
IF TMS IS USED FOR VR1, GPU
CPU
LOAD
GPU
LOAD
6 FN6964.0
January 3, 2011

6 Page









ISL6366 pdf, datenblatt
ISL6366
resistor value can be effectively set at 60Ω to 1.8kΩ. When VR0
is disabled (PWM1 = VCC), connect 1MΩ from this pin to GND.
ISENS+, ISENS - The ISENS+ and ISENS- pins are current sense
inputs to the differential amplifier of VR1. The sensed current is
used for overcurrent protection and droop regulation. For DCR
sensing, connect each ISENS- pin to the node between the RC
sense elements. Tie the ISENS+ pin to the other end of the sense
capacitor through a resistor, RISENS. The voltage across the
sense capacitor is proportional to the inductor current. Therefore,
the sense current is proportional to the inductor current and
scaled by the DCR of the inductor and RISENS. When VR1 is
disabled, have ISENS- grounded and ISENS+ open.
IMON - IMON is the output pin of sensed, thermally compensated (if
internal thermal compensation is used) average current of VR0. The
voltage at the IMON pin is proportional to the load current and the
resistor value, and internally clamped to 1.12V. If the clamped
voltage is triggered, it will initiate an overcurrent shutdown. By
choosing the proper value for the resistor at IMON pin, the
overcurrent trip level can be set to be lower than the fixed internal
overcurrent threshold. During the dynamic VID, the OCP function of
this pin is disabled to avoid false triggering. Tie it to GND if not used.
Does not need to refer to the remote ground for VR12/IMPV7
applications.
FS_DRP - A resistor placed from this pin to GND/VCC will set the
switching frequency of VR0. The relationship between the value
of the resistor and the switching frequency will be approximated
by Equation 4 on page 16. This pin is also used to set the droop
option. The droop is disabled when the resistor is pulled to VCC
and enabled when the resistor is pulled to ground. When VR0 is
disabled (PWM1 = VCC), connect 1MΩ from this pin to GND.
HFCOMP - Connect a resistor with a similar value of the feedback
impedance to the VR0 output to compensate the level-shifted
output voltage during high-frequency load transient events.
Connecting more than 2x of feedback impedance to this pin or
keeping it open virtually disables this feature.
PSICOMP - Connect an RC to the type III compensation capacitor
of the VR0 output voltage. This improves loop gain and load
transient response in PSI1/2/3/Decay mode. An open pin will
disable this feature.
SICI - When this pin ispulled to ground, it sets for standard inductor
(SI) operation;when this pin is pulel d to VCC, itsets coupled-inductor
(CI) operation. Thephase dropping operation optionsfor PSI1/2/3
mode are summarized in Table 3 on page 16.
DVC - A series resistor and capacitor can be connected from this
pin to the FB pin to compensate and smooth dynamic VID
transitions.
VSENS, RGNDS, FBS, COMPS, VR_RDYS, IMONS, FSS_DRPS,
HFCOMPS - These pins are for VR1 regulator and have the same
function as VSEN, RGND, FB, COMP, VR_RDY, IMON, FS_DRP, and
HFCOMP, respectively. However, HFCOMPS has multiplexed the
DVCS function, while the FSS_DRPS does have additional
programming feature as described in the following.
HFCOMPS/DVCS - Connect a resistor with a similar value of the
feedback impedance to the VR1 output to compensate the level-
shifted output voltage during high-frequency load transient
events. Connecting more than 2x of feedback impedance to this
pin or keeping it open virtually disables this feature. If the droop
option of VR1 is disabled, then this pin becomes DVCS. A series
resistor and capacitor can be connected from this pin to the FBS
pin to compensate and smooth dynamic VID transitions for VR1
output.
FSS_DRPS - A resistor placed from this pin to ground/VCC will set
the switching frequency of VR1. The relationship between the
value of the resistor and the switching frequency will be
approximated by Equation 4 on page 16. This pin is also used to
set the droop option. The droop is disabled when the resistor is
pulled to VCC and enabled when the resistor is pulled to ground.
When VR1 is disabled (PWMS = VCC), connect 1MΩ from this pin
to GND for ADDR: 0, 2, 4, and 6; to VCC for ADDR: 8, A, and C.
TMS - This is an input pin for the temperature monitoring. Connect
this pin through an NTC thermistor to GND and a resistor to VCC of
the controller. The voltage at this pin is inversely proportional to
the VR temperature. The thermal information can be used for VR1
thermal compensation. If TCOMPS is set at “OFF” bit, the
integrated thermal compensation is disabled; otherwise, the
thermal information is used for VR1 thermal compensation with
“TCOMPS” data. Combined with TM pin, thethermal information at
TMS pin will also be used to trigger VR_HOT#. The NTC should be
placed close to the current sensing element, theoutput inductor or
dedicated sense resistor of VR1. If not used, connect this pin to TM
or 1MΩ/2MΩ resistor divider, but DON’T tie it to VCC or GND.
SVCLK - An input pin for a synchronous clock signal of SerialVID
bus from CPU.
SVDATA - An input pin for transferring open-drain data signals
between CPU and VR controller.
SVALERT# - An output pin for transferring the active low signal
driven asynchronously from the VR controller to CPU.
RAMP_ADJ - An input pin to set the slope of Sawtooth for VR0.
The slope of the Sawtooth is proportional to the current, sampled
by the an active pull-down device, into this pin. When the resistor
is connected to the input voltage of the VR0, the slope will be
proportional to the input voltage, achieving voltage feed-forward
compensation. For a 12V supply (VIN) and 2.4MΩ pull up (~ 5µA),
it sets a nominal 0.25V/µs up-ramp slope at 500kHz switching
frequency, corresponding to 0.5V peak-to-peak up ramp. The
maximum peak-to-peak up ramp should be limited to 3V,
corresponding a pull-down current of 30µA at 500kHz, i.e., the
pull-up impedance should be higher than VIN/30µA at 500kHz.
See Equation 3 for the up ramp amplitude calculation. When this
pin is floating, the up ramp amplitude sets to 1V regardless of
the switching frequency and the feedforward function is
disabled.
ADDR_IMAXS_TMAX, BTS_DES_TCOMPS, BT_FDVID_TCOMP,
NSPI_DE_IMAX - These are four register pins to program system
parameters. The meaning of each is described as below. See
Table 9 for the summary.
ADDR_IMAXS_TMAX (0C):
ADDR - An input pin to set the address offset register of VR0 (0,
2, 4, 6, 8, A, C) and VR1 (1, 3, 5, 7). E/F is an ALL call address
and is not used.
12 FN6964.0
January 3, 2011

12 Page





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