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74LS163 Schematic ( PDF Datasheet ) - SYC

Teilenummer 74LS163
Beschreibung BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS
Hersteller SYC
Logo SYC Logo 




Gesamt 6 Seiten
74LS163 Datasheet, Funktion
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The
LS161A and LS163A count modulo 16 (binary.)
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge.
BCD (Modulo 10)
Binary (Modulo 16)
Asynchronous Reset
LS160A
LS161A
Synchronous Reset
LS162A
LS163A
Synchronous Counting and Loading
Two Count Enable Inputs for High Speed Synchronous Expansion
Terminal Count Fully Decoded
Edge-Triggered Operation
Typical Count Rate of 35 MHz
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
1 2 3 4 56 78
*R CP P0 P1 P2 P3 CEP GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
*MR for LS160A and LS161A
*SR for LS162A and LS163A
PIN NAMES
PE
P0 – P3
CEP
CET
CP
MR
SR
Q0 – Q3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
Terminal Count Output (Note b)
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and
Temperature Ranges.
LOADING (Note a)
HIGH
LOW
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 U.L. for Commercial (74)
74LS160
74LS161
74LS162
74LS163
BCD DECADE COUNTERS /
4-BIT BINARY COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
934 56
7
PE P0 P1 P2 P3
CEP
10 CET
TC 15
2 CP
*R Q0 Q1 Q2 Q3
1 14 13 12 11
VCC = PIN 16
GND = PIN 8
*MR for LS160A and LS161A
*SR for LS162A and LS163A
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74LS163 Datasheet, Funktion
SN54/74LS160A SN54/74LS161A
SN54/74LS162A SN54/74LS163A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
CET 1.3 V
1.3 V
The positive TC pulse occurs when the outputs are in the
(Q0 Q1 Q2 Q3) state for the LS160 and LS162 and the
(Q0 Q1 Q2 Q3) state for the LS161 and LS163.
tPLH
TC 1.3 V
tPHL
1.3 V
Figure 3
OTHER CONDITIONS: CP = PE = CEP = MR = H
CLOCK TO TERMINAL COUNT DELAYS
The positive TC pulse is coincident with the output state
(Q0 Q1 Q2 Q3) state for the LS161 and LS163 and
(Q0 Q1 Q2 Q3) for the LS161 and LS163.
CP
Figure 4
TC
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: PE = CEP = CET = MR = H
SETUP TIME (ts) AND HOLD TIME (th)
FOR PARALLEL DATA INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(H)
P0 P1 P2 P3
1.3 V
th(H) = 0 ts(L)
1.3 V 1.3 V
1.3 V
th(L) = 0
1.3 V
Q0 Q1 Q2 Q3
Figure 5
OTHER CONDITIONS: PE = L, MR = H
SETUP TIME (ts) AND HOLD TIME (th) FOR
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(L)
SR or PE
1.3 V 1.3 V
th (L) = 0 ts(H)
th(H) = 0
1.3 V
PARALLEL LOAD
(See Fig. 5)
1.3 V
COUNT MODE
(See Fig. 7)
Q RESPONSE TO PE
RESET
COUNT OR LOAD
Q RESPONSE TO SR
Figure 6
CP
ts(H)
CEP
ts(H)
CET 1.3 V
1.3 V
ts(L)
th(H) = 0
1.3 V
th(H) = 0
1.3 V
COUNT
1.3 V
th(L) = 0
1.3 V
ts(L)
HOLD
1.3 V
1.3 V
th(L) = 0
1.3 V
HOLD
Q
OTHER CONDITIONS: PE = H, MR = H
Figure 7
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