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2128E Schematic ( PDF Datasheet ) - LatticeSemiconductor

Teilenummer 2128E
Beschreibung In-SystemProgrammableSuperFASTHighDensityPLD
Hersteller LatticeSemiconductor
Logo LatticeSemiconductor Logo 




Gesamt 11 Seiten
2128E Datasheet, Funktion
ispLSI® 2128E
In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
Output Routing Pool (ORP)
Output Routing Pool (ORP)
— 6000 PLD Gates
D7 D6 D5 D4 D3 D2 D1 D0
— 128 I/O Pins, Eight Dedicated Inputs
A0
C7
— 128 Registers
— High Speed Global Interconnect
A1
C6
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
A2
DQ
C5
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
ispLSI 2128 Devices
A3
A4
Logic
Array
DQ
DQ
GLB
C4
C3
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay
A5
A6
DQ
C2
C1
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
A7 Global Routing Pool (GRP) C0
— ispJTAG™ In-System Programmable via IEEE 1149.1
B0 B1 B2 B3 B4 B5 B6 B7
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed-
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Voltage Systems
0139(9A)/2128
— PCI Compatible Outputs
— Open-Drain Output Option
Description
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
— Superior Quality of Results
of any GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
The device also has 128 I/O cells, each of which is
Tools, Timing Simulator and ispANALYZER™
directly connected to an I/O pin. Each I/O cell can be
— PC and UNIX Platforms
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 1998
2128e_02
1






2128E Datasheet, Funktion
Specifications ispLSI 2128E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
-180
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. UNITS
Inputs
tio 20 Input Buffer Delay
tdin 21 Dedicated Input Delay
GRP
tgrp 22 GRP Delay
GLB
t4ptbpc
t4ptbpr
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
tgsu
tgh
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
tgco
31 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
36 ORP Delay
37 ORP Bypass Delay
Outputs
tob 38 Output Buffer Delay
tsl 39 Output Slew Limited Delay Adder
toen
todis
tgoe
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
Clocks
tgy0
tgy1/2
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset
tgr 45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
0.5
1.1
0.5 0.5
1.7 2.2
ns
ns
0.6 1.2 1.7 ns
1.9
2.9
3.9
3.9
3.9
0.0
0.7
3.3
0.3
0.6
4.8
5.9
1.0 4.0
3.7 5.8
4.2 5.8
5.2 6.8
5.2 7.3
5.2 8.0
0.5 0.5
0.7 1.2
4.3 4.0
0.3 0.3
1.1 1.3
6.0 6.1
6.9 8.6
2.5 5.5 4.1 7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.9
0.4
1.0 1.4
0.5 0.4
ns
ns
1.6
1.5
3.0
3.0
2.0
1.6 1.6 ns
1.5 10.0 ns
3.4 4.2 ns
3.4 4.2 ns
3.6 4.8 ns
0.7 0.7
0.9 0.9
1.6 1.6 2.7 2.7
1.8 1.8 2.7 2.7
ns
ns
4.4
6.3 9.2 ns
Table 2-0036A/2128E
6

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