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PDF NB3W1200L Data sheet ( Hoja de datos )
| Número de pieza | NB3W1200L | |
| Descripción | 3.3V 100MHz - 133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB - Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3N1200K, NB3W1200L
3.3 V 100/133 MHz
Differential 1:12 HCSL or
Push-Pull Clock ZDB/Fanout
Buffer for PCle
Description
The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable
Memory Interconnect (Intel SMI) applications. The VCO of the
device is optimized to support 100 MHz and 133 MHz frequency
operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power
NMOS Push−Pull buffer type.
Features
• 12 Differential Clock Output Pairs @ 0.7 V
• HCSL Compatible Outputs for NB3N1200K
• Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
• Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
• DB1200Z and DB1200ZL Compliant
• 3.3 V ±5% Supply Voltage Operation
• Fixed−Feedback for Lowest Input−To−Output Delay Variation
• SMBus Programmable Configurations to Allow Multiple Buffers in a
Single Control Network
• PLL Bypass Configurable for PLL or Fanout Operation
• Programmable PLL Bandwidth
• 2 Tri−level Addresses Selection (9 SMBUS Addresses)
• Individual OE Control Pin for Each of 12 Outputs
• Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
• 50 ps Max Output−to−Output Skew Performance
• 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
• 100 ps Input to Output Delay Variation Performance
• QFN 64−pin Package, 9 mm x 9 mm
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
• 0°C to +70°C Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
64 1
QFN64
MN SUFFIX
CASE 485DH
MARKING DIAGRAMS
1
NB3N
1200K
AWLYYWWG
1
NB3W
1200L
AWLYYWWG
NB3x1200x= Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping†
NB3N1200KMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3N1200KMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
NB3W1200LMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3W1200LMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 1
1
Publication Order Number:
NB3N1200K/D
1 page  
NB3N1200K, NB3W1200L
Table 1. NB3N1200K PIN DESCRIPTIONS
Pin Number
Pin Name
Type
34
DIF_4
O, DIF
35
DIF_4#
O, DIF
36
OE_4#
I, SE
37
OE_5#
I, SE
38
DIF_5
O, DIF
39
DIF_5#
O, DIF
40
VDD
3.3 V
41
GND
GND
42
DIF_6
O, DIF
43
DIF_6#
O, DIF
44
OE_6#
I, SE
45
OE_7#
I, SE
46
DIF_7
O, DIF
47
DIF_7#
O, DIF
48
GND
GND
49
VDD
3.3 V
50
DIF_8
O, DIF
51
DIF_8#
O, DIF
52
OE_8#
I, SE
53
OE_9#
I, SE
54
DIF_9
O, DIF
55
DIF_9#
O, DIF
56
VDD
3.3 V
57
VDD
3.3 V
58
GND
GND
59
DIF_10
O, DIF
60
DIF_10#
O, DIF
61
OE_10#
I, SE
62
OE_11#
I, SE
63
DIF_11
O, DIF
64
DIF_11#
O, DIF
EP
Exposed Pad
Thermal
Description
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 4.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 5.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
Ground for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 6.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 7.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
3.3 V power supply for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 8.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 9.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
3.3 V power supply for outputs.
Ground for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 10.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 11.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
The Exposed Pad (EP) on the QFN−64 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die,
and must be electrically and thermally connected to GND on the PC board.
www.onsemi.com
5
5 Page 
NB3N1200K, NB3W1200L
Table 9. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode)
(VDD = VDDA = VDDR = 3.3 V ±5%)
CLK = 100 MHz, 133.33 MHz
Symbol
Parameter
Min Max
Tstab (Note 44)
Clock Stabilization Time
1.8
Unit
ms
Laccuracy (Notes 26, 30, 38, 45)
Long Accuracy
100 ppm
Tabs (Notes 26, 27, 30)
Absolute
Min/Max
Host CLK
Period
No Spread
−0.5% Spread
9.94900 for 100 MHz
7.44925 for 133 MHz
9.49900 for 100 MHz
7.44925 for 133 MHz
10.05100 for 100 MHz
7.55075 for 133 MHz
10.10126 for 100 MHz
7.58845 for 133 MHz
ns
Slew_rate (Notes 24, 26, 30)
DIFF OUT Slew_rate (see Figure 4)
1.0
4.0 V/ns
DTrise / DTfall (Notes 26, 29, 40)
Rise and Fall Time Variation
125 ps
Rise/Fall Matching (Notes 26, 30, 41, 43)
20 %
VHigh (Notes 26, 29, 32)
Voltage High (typ 0.70 Volts)
660
850 mV
VLow (Notes 26, 29, 33)
Voltage Low (typ 0.0 Volts)
−150
150 mV
Vmax (Note 29)
Maximum Voltage
1150
mV
Vcross absolute (Notes 23, 25, 26, 29, 36) Absolute Crossing Point Voltages
250
550 mV
Vcross relative (Notes 26, 28, 29, 36) Relative Crossing Point Voltages
Calc
Calc
Total D Vcross (Notes 26, 29, 37)
Total Variation of Vcross
Over All Edges
140 mV
Tccjitter (Notes 26, 30, 42)
Cycle−to−Cycle Jitter
50 ps
Duty Cycle (Notes 26, 30)
PLL and Bypass Modes
45
55 %
tOE# Latency
OE# Latency − DIFF start after OE#
Assertion
− DIFF stop after OE# Deassertion
4
12 Clocks
Vovs (Notes 26, 29, 34)
Maximum Voltage (Overshoot)
Vhigh + 0.3
V
Vuds (Notes 26, 29, 35)
Maximum Voltage (Undershoot)
Vlow − 0.3
V
Vrb (Notes 26, 29)
Ringback Voltage 0.2 N/A V
23. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
24. Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the
differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge
Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall.
25. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
26. Test configuration is Rs = 33.2 W, Rp = 49.9, 2 pF for 100 W transmission line; Rs = 27 W, Rp = 42.2, 2 pF for 85 W transmission line.
27. The average period over any 1 ms period of time must be greater than the minimum and less than the maximum specified period.
28. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700
– Vhavg), (see Figure 7).
29. Measurement taken from Single Ended waveform.
30. Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%.
31. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
32. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
33. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
34. Overshoot is defined as the absolute value of the maximum voltage.
35. Undershoot is defined as the absolute value of the minimum voltage.
36. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
37. DVcross is defined as the total variation of all crossing voltages of Rising DIFF and Falling DIFF#. This is the maximum allowed variance
in Vcross for any particular system.
38. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz.
39. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz.
40. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
41. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIFF versus the falling edge rate
(average) of DIFF#. Measured in a ±75 mV window around the crosspoint of DIFF and DIFF#.
42. Measured with device in PLL mode, in BYPASS mode jitter is additive.
43. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
44. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks
are output from the buffer chip (PLL locked).
45. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy
requirements. The NB3N1200K and NB3W1200L itself do not contribute to ppm error.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet NB3W1200L.PDF ] | |
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