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Teilenummer | NB3N1200K |
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Beschreibung | 3.3V 100MHz - 133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB - Fanout Buffer | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 26 Seiten NB3N1200K, NB3W1200L
3.3 V 100/133 MHz
Differential 1:12 HCSL or
Push-Pull Clock ZDB/Fanout
Buffer for PCle
Description
The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable
Memory Interconnect (Intel SMI) applications. The VCO of the
device is optimized to support 100 MHz and 133 MHz frequency
operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power
NMOS Push−Pull buffer type.
Features
• 12 Differential Clock Output Pairs @ 0.7 V
• HCSL Compatible Outputs for NB3N1200K
• Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
• Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
• DB1200Z and DB1200ZL Compliant
• 3.3 V ±5% Supply Voltage Operation
• Fixed−Feedback for Lowest Input−To−Output Delay Variation
• SMBus Programmable Configurations to Allow Multiple Buffers in a
Single Control Network
• PLL Bypass Configurable for PLL or Fanout Operation
• Programmable PLL Bandwidth
• 2 Tri−level Addresses Selection (9 SMBUS Addresses)
• Individual OE Control Pin for Each of 12 Outputs
• Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
• 50 ps Max Output−to−Output Skew Performance
• 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
• 100 ps Input to Output Delay Variation Performance
• QFN 64−pin Package, 9 mm x 9 mm
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
• 0°C to +70°C Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
64 1
QFN64
MN SUFFIX
CASE 485DH
MARKING DIAGRAMS
1
NB3N
1200K
AWLYYWWG
1
NB3W
1200L
AWLYYWWG
NB3x1200x= Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping†
NB3N1200KMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3N1200KMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
NB3W1200LMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3W1200LMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 1
1
Publication Order Number:
NB3N1200K/D
NB3N1200K, NB3W1200L
Table 2. NB3W1200L PIN DESCRIPTIONS
Pin Number
Pin Name
Type
1
VDDA
3.3 V
2
GNDA
GND
3 NC I/O
4
100M_133M#
I, SE
5
HBW_BYPASS_LBW#
I, SE
6
PWRGD / PWRDN#
I
7
GND
GND
8
VDDR
VDD
9
CLK_IN
I, DIF
10
CLK_IN#
I, DIF
11
SA_0
I
12
SDA
I/O
13 SCL I/O
14
SA_1
I
15 NC I/O
16 NC I/O
17
DIF_0
O, DIF
18
DIF_0#
O, DIF
19
OE_0#
I, SE
20
OE_1#
I, SE
21
DIF_1
O, DIF
22
DIF_1#
O, DIF
23
GND
GND
24
VDD
3.3 V
25
VDD_IO
VDD
26
DIF_2
O, DIF
27
DIF_2#
O, DIF
28
OE_2#
I, SE
29
OE_3#
I, SE
30
DIF_3
O, DIF
31
DIF_3#
O, DIF
32
VDD_IO
VDD
33
GND
GND
Description
3.3 V Power Supply for PLL.
Ground for PLL.
No Connect
3.3 V tolerant inputs for input/output Frequency Selection (FS). An external pull−
up or
pull−down resistor is attached to this pin to select the input/output frequency.
High = 100 MHz Output
Low = 133 MHz Output
Tri−Level input for selecting the PLL bandwidth or bypass mode
(refer to tri− level threshold in Table 4).
High = High BW mode, Med = Bypass mode,
Low = Low BW mode
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
3.3 V power supply for receiver.
0.7 V Differential True input
0.7 V Differential Complementary input
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
Open collector SMBus data.
SMBus slave clock input.
3.3 V LVTTL input selecting the address. Tri−level input
(refer to tri−level threshold in Table 4.)
No Connect. There are active signals on pin 15;
do not connect anything to this pin.
No Connect. There are active signals on pin 16;
do not connect anything to this pin.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 0.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 1.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
3.3 V power supply for core.
Power supply for differential outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 2.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 3.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Power supply for differential outputs.
Ground for outputs.
www.onsemi.com
6
6 Page NB3N1200K, NB3W1200L
Table 10. CLOCK PERIOD SSC DISABLED
SSC OFF
Center
Freq.
MHz
1 Clock
− Jitter c−c
Abs Per Min
1 ms
− SSC Short
Avg Min
Measurement Window
0.1 s
0.1 s
0.1 s
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
100.00
9.94900
9.99900
10.00000
10.00100
133.33
7.44925
7.49925
7.50000
7.50075
1 ms
+ SSC Short
Avg Max
1 Clock
+ Jitter c−c
Abs Per Max
10.05100
7.55075
Units
ns
ns
Table 11. CLOCK PERIOD SSC ENABLED
SSC ON
Center
Freq.
MHz
1 Clock
− Jitter c−c
Abs Per Min
1 ms
− SSC Short
Avg Min
Measurement Window
0.1 s
0.1 s
0.1 s
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
99.75
9.94900
9.99900
10.02406
10.02506
10.02607
133.00
7.44925
7.49925
7.51805
7.51880
7.51955
1 ms
+ SSC Short
Avg Max
10.05126
7.53845
1 Clock
+ Jitter c−c
Abs Per Max
10.10126
7.58845
Units
ns
ns
Table 12. INPUT EDGE RATE (Note 46)
Frequency Select (FS)
Min
Max
Unit
100 MHz
0.35
N/A
V/ns
133 MHz
0.35
N/A
V/ns
46. Input edge rate is based on single ended measurement. This is the minimum input edge rate at which the NB3N1200K / NB3W1200L devices
are guaranteed to meet all performance specifications.
www.onsemi.com
12
12 Page | ||
Seiten | Gesamt 26 Seiten | |
PDF Download | [ NB3N1200K Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
NB3N1200K | 3.3V 100MHz - 133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB - Fanout Buffer | ON Semiconductor |
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