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PDF ML7029 Data sheet ( Hoja de datos )
| Número de pieza | ML7029 | |
| Descripción | Multifunction ADPCM CODEC | |
| Fabricantes | LAPIS | |
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ML7029
Multifunction ADPCM CODEC
FEDL7029-04
Issue Date: Jun. 8, 2007
GENERAL DESCRIPTION
The ML7029 is a single cha nnel ADPCM CODEC IC which performs mutual transcoding between the analog
voice band signal and 32 kbps ADPCM serial data.
FEATURES
Single 3 V Power Supply Operation (VDD: 2.7 to 3.6 V)
ADPCM Algorithm:
ITU-T G.726 (32 kbps, 24 kbps, 16 kbps)
Full-Duplex Transmit/Receive Operation
Transmit/Receive Synchronous Mode Only
PCM Data Format:
-law
Serial PCM/ADPCM Transmission Data Rate:
64 kbps to 2048 kbps (when SYNC = 8 kHz)
Low Power Consumption
Operating Mode:
Power-Down Mode:
Sampling Frequency:
18 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz)
0.03 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz)
6 kHz to 21 kHz selectable (However, there are
limitations to 16 kHz or higher frequencies)
Master Clock Frequency:
Sampling frequency 1296
When SYNC = 8 kHz: 10.368 MHz
Transmit/Receive Mute, Transmit/Receive Programmable Gain Control
Side Tone Path with Programmable Attenuation (8-Step Level Adjustment)
Serial MCU Interface Control
Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (ML7029)
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http://www.Datasheet4U.com
1 page  
FEDL7029-04
ML7029
MCK
Master clock input.
The frequency is 1296 times the SYNC signal. For e xample, it is 1 0.368 MHz when the SYNC signal is 8 kHz.
The master clock signal may be asynchronous with BCLK and SYNC.
PCMSO
Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLK and XSYNC.
Refer to Figure 1. During power-down, the PCMSO output is at “L” level.
PCMSI
Transmit PCM data input.
This signal is converted to the transmit ADPCM data, PCM is shifted in synchronization with the falling edge of
BCLK. Normally, this pin is connected to PCMSO. Refer to Figure 1.
PCMRO
Receive PCM data output.
PCM is th e ou tput sign al after ADPCM decoder pro cessing. Th is sig nal is ou tput serially fro m MSB in
synchronization with the rising edge of BCLK and RSYNC. Refer to Figure 1.
During power-down, the PCMRO output is at “L” level.
PCMRI
Receive PCM data input.
PCM is shifted on the rising edge of the BCLK and input from MSB. Normally, this pin is connected to PCMRO.
Refer to Figure 1.
IS
Transmit ADPCM signal output.
After having encoded PCM with ADPCM, the signal is output from MSB in synchronization with the rising edge
of BCLK and XSYNC. Refer to Figure 1. This pin is at “H” level during power-down.
IR
Receive ADPCM signal input.
This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure
1.
BCLK
Shift clock input for the PCM and ADPCM data.
The frequency is set in the range of 8 to 256 times the SYNC frequency. Refer to Figure 1.
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5 Page 
FEDL7029-04
ML7029
AC Characteristics
Parameter S
ymbol
Condition
Freg. (Hz)
(V DD = 2.7 to 3.6 V, Ta = –25 to +70C)
Min. T yp. Max. Unit
Level (dBm0)
Transmit Frequency
Response
SYNC = 8 kHz
BPF
LB8T1
LB8T2
LB8T3
LB8T4
LB8T5
60 30
300 –0.5
1015 Refere
3400 –0.5
3970
— — dB
— 1.5 dB
0 nce dB
— 1.0 dB
12 —
— dB
Transmit Frequency
Response
SYNC = 11.025 kHz
BPF
LB11T1
LB11T2
LB11T3
LB11T4
LB11T5
60 30
300 –0.5
1400 Refere
4690 –0.5
5470
— — dB
— 1.5 dB
0 nce dB
— 1.0 dB
12 —
— dB
Transmit Frequency
Response
SYNC = 8 kHz
LPF
LL8T1
LL8T2
LL8T3
LL8T4
300 –0.5
1015 Refere
3400
3970
— 0.5 dB
0
nce dB
–0.5 — 1.0 dB
12 —
— dB
Transmit Frequency
Response
SYNC = 11.025 kHz
LPF
LL11T1
LL11T2
LL11T3
LL11T4
300 –0.5
1400 Refere
4690
5470
— 0.5 dB
0
nce dB
–0.5 — 1.0 dB
12 —
— dB
Receive Frequency
Response
SYNC = 8 kHz
LPF
LL8R1
LL8R2
LL8R3
LL8R4
300 –0.5
1015 Refere
3400
3970
— 0.5 dB
0
nce dB
–0.5 — 1.0 dB
12 —
— dB
Receive Frequency
Response
SYNC = 11.025 kHz
LPF
LL11R1
LL11R2
LL11R3
LL11R4
300 –0.5
1400 Refere
4690
5470
— 0.5 dB
0
nce dB
–0.5 — 1.0 dB
12 —
— dB
Transmit S/N Ratio
SYNC = 8 kHz (*3)
SD8T1
SD8T2
f = 1015 Hz
3
–40 28
35
— — dB
— — dB
Receive S/N Ratio
SYNC = 8 kHz (*3)
SD8R1
SD8R2
f = 1015 Hz
3
–40 28
35
— — dB
— — dB
Transmit S/N Ratio
SYNC = 16 kHz (*3)
SD16T1
SD16T2
f = 1015 Hz
3
–40 28
35
— — dB
— — dB
Receive S/N Ratio
SYNC = 16 kHz (*3)
SD16R1
SD16R2
f = 1015 Hz
3
–40 28
35
— — dB
— — dB
Idle Channel Noise
SYNC = 8 kHz (*3)
NIDLT
NIDLR
—
AIN– = SG
(*4) —
——
—
–68 dBm0pP
–72 dBm0pP
Idle Channel Noise
SYNC = 16 kHz (*3)
NIDLT
NIDLR
—
AIN– = SG
(*4) —
——
—
–68 dBm0pP
–72 dBm0pP
Absolute Signal
AVT 1015 Hz(GSX) SYNC = 8 kHz
Amplitude (* 5)
AVR 1015 Hz(VFRO) SYNC = 8 kHz
*3: Use the P-message weighted filter
*4: PCMRI input code “11111111” (µ-law)
0 0.285 0.320 0.359 Vrms
0 0.285
0.320 0.359 Vrms
*5: 0.320 Vrms = 0 dBm0 = –7.7 dBm (600)
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