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PDF ML7005 Data sheet ( Hoja de datos )
| Número de pieza | ML7005 | |
| Descripción | DTMF Transceiver | |
| Fabricantes | LAPIS | |
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ML7005
DTMF Transceiver
FEDL7005-01
Issue Date: Oct. 18, 2011
GENERAL DESCRIPTION
The ML7005 is a multi-functional DTMF transceiver LSI with built-in a DTMF signal generator, a
DTMF signal receiver, a call progress tone generator, a call progress tone detector, and a FAX (FX)
signal detector.
Each functional block can be controlled by an external MCU via a 4-bit processor interface.
The ML7005 does not contains a modem.
However, the DTMF system data transmission is possible at less than 66 bps by setting the DTMF
receiver to the high-speed detection mode.
The ML7005 operates with low-power consumption and is suitable for remote control systems,
especially for ACR (Automatic Cost Routing) controllers.
FEATURES
• Wide range of power supply voltage : +2.7 V to +5.5 V
• Low power consumption
Operating mode : 4.0 mA (VDD = 3 V) Typ.
Operating mode : 5.0 mA (VDD = 5 V) Typ.
Power down mode : 1 mA Typ.
• The 4-bit processor interface supports both the Intel processor mode in which a read signal and
a write signal are used independently of each other, and the Motorola processor mode in which
a read signal and a write signal are used in common.
• The DTMF receiver can select either the high-speed detection mode (signal repeat time: more than
60 ms) or the normal detection mode (signal repeat time: more than 90 ms).
• Built-in call progress tone generator
• Built-in FAX signal (FX: 1300 Hz) detector
• The DTMF signal generator, DTMF signal detector, call progress tone generator, and call progress
tone detector can operate concurrently.
• Built-in 3.579545 MHz crystal oscillator circuit
• Package :
32- pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7005MB)
1/25
http://www.Datasheet4U.com
1 page  
FEDL7005-01
ML7005
Symbol Pin
READB 14
CSB
15
ALE 16
WRB 17
D3 to D0 18 to 21
Type
IN
IN
IN
IN
I/O
Description
Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the read control input pin.
When this pin is set to "0", data in the specified register is output to the
bus lines (D3 to D0).
At that time, CSB must be "0".
See the figure 4 for processor interface timing.
When PTYPE is "0" (Motorola processor mode) :
This pin is the clock input pin (equivalent to SCLK of the MSM7524).
When in Write mode, data in D3 to D0 is written to the specified register
at the falling edge of the READB signal.
When in Read mode, data in the specified register is output to D3 to D0
when the READB signal is "1", and D3 to D0 is opened when the
READB signal is "0".
The READB signal is not necessarily a periodical signal.
See the figure 5 for processor interface timing.
Chip select input pin for processor interface.
When the CSB signal is "0", read and write operations are possible.
When the CSB signal is "1", read and write operations are impossible.
Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the address latch enable input pin.
The register address data in D1 to D0 is latched at the falling edge of
ALE.
When PTYPE is "0" (Motorola processor mode) :
This pin is the address data input pin (equivalent to AD0 of the
M SM7524).
When this pin is "1", data can be written to the control register (CR) and
data can be read from the status register (STR).
When this pin is "0", data can be written to the DTMF transmit register
(DTMFT) and data can be read from the DTMF receive register
(DTMFR).
Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the Write control input.
Data in the data bus lines (D3 to D0) is written to the specified register.
At that time, CSB must be "0".
When PTYPE is "0" (Motorola processor mode) :
This is the signal input pin for controlling the Read and Write modes
(equivalent to R/W of the MSM7524).
When this pin is "1", the LSI enters the Read mode.
When this pin is "0", the LSI enters the Write mode.
4-bit data bus I/O pins for processor interface.
When PTYPE is "1" (Intel processor mode), D1 and D0 are also used for
addressing.
5/25
5 Page 
FEDL7005-01
ML7005
AC Characteristics 5 DTMF Receiver
Parameter
DTMF Detect
Amplitude
DTMF Non-detect
Amplitude ル
Detect Frequency
Non-detect
Frequency
Level Twist
Noise to Signal
Ratio
Dial Tone Rejection
Ratio
Signal Repetition
Time
Time to Detect
Time to Reject
Interdigit Pause
Time
Acceptable Drop
Out Time
Detect Delay Time
Symbol
VDETDT1
VDETDT2
VREJFX
Condition
(VDD=+2.7 to +5.5 V, Ta=-30 to +85°C)
Min. Typ. Max. Unit
2.7V VDD 5.5V
-42
—
-10
4.5V VDD 5.5V
-42 —
0 dBm
Per Frequency at DTRIO
——
-60
fDETDT -1.8
fREJDT To Nominal Frequency
VTWIST VHigh Group - VLow Group
+3.8 —
——
-6.0 —
—
+1.8
—
-3.8
+6.0
%
dB
VNIS N/S(N：0.3 to 3.4kHz)
— -12
— dB
VREJDT
tCYCDT0
tCYCDT1
tDETDT0
tDETDT1
tREJDT0
tREJDT1
tPOSDT0
tPOSDT1
tBRKDT10
tBRKDT11
tBRKDT20
tBRKDT21
tDELDT0
360 to 440Hz
Detect
Non-detect
*1
SPB="1"
(Before output)
SPB="0"
(During output)
DTTIM="1"
DTTIM="0"
DTTIM="1"
DTTIM="0"
DTTIM="1"
DTTIM="0"
DTTIM="1"
DTTIM="0"
DTTIM="1"
DTTIM="0"
DTTIM="1"
DTTIM="0"
DTTIM="1"
—
60
90
35
49 —
—
——
21
30 —
—
——
—
——
12
45
—
—
—
—
—
—
—
26
41
— dB
—
—
—
—
10
24
—
—
0.4
0.4
3 ms
10
37
tDELDT1
DTTIM="0"
24
49
Detect Hold Time
SPB Delay Time
tHOLDT0
tHOLDT1
tSP
DTTIM="1"
DTTIM="0"
DTTIM="1", "0"
15
24
0.2
20
28
0.6
*1 See the figure 3 for timing.
The input level includes the entire range indicated in VDETDT1 and VDETDT2.
The input frequency includes the entire range indicated in fDETDT.
27
35
1.0
11/25
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