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AN2633 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer AN2633
Beschreibung STR91xFA low power management and power consumption Application note
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
AN2633 Datasheet, Funktion
AN2633
Application note
STR91xFA low power management
and power consumption
Introduction
Power consumption is a significant issue for developers of embedded systems today.
Whether the target application is a cellphone, MP3 player, remote control, bio-medical
device or one of a whole new generation of electronic products, it is very likely that efficient
power management and low current consumption are on top of the list of design goals. In
terms of low power design techniques, more and more embedded designers use dynamic
control of clocks and frequencies. For this reason, this application note focuses on this in the
context of the STR91xFA microcontroller family.
This application note is intended for system designers who require a hardware
implementation overview of the STR91xFA low power modes. It includes details on the
power supply circuitry and components, clock systems, register settings and power
management. This guideline document is intended to show how to make the best use of the
extensive low power features of the STR91xFA microcontroller family,
Software source files can be downloaded with this application note for testing the STR91xFA
power modes.
January 2008
Rev 1
1/48
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AN2633 Datasheet, Funktion
Power supply and clocks
AN2633
When the STR91xFA is in low power mode, you can also put the Flash in Power Down mode
for even lower power consumption. You do this by programming the PWD bit in the Flash
Configuration register. The consumption is drastically reduced, but after wake-up from low
power, a delay is inserted automatically to ensure the Flash is operational before the CPU
starts execution.
1.3
1.3.1
1.3.2
1.3.3
Clocks
External clock sources:
fOSC: A 4 to 25 MHz oscillator provides the main operating clock for all on-chip functional
blocks.
fRTC:The RTC has an independent 32.768 kHz crystal. The RTC keeps on running even
when the CPU is in power down or power off mode. This slow RTC clock can also be used in
power management.
fUSB: fUSB input clock is not mandatory to generate the 48 MHz for USB clock. It is needed
when the PLL is configured to generate a clock that cannot be shared by the USB. The PLL
is able to generate a 48 or 96 MHz clock from the input crystal frequency for internal use by
selecting the appropriate multiplier and divider.
fTIMEXT: The TIM Timer/counters can run on the internal peripheral clock or the external
TIMEXT input clock. You select this by programming the TIM01SEL and TIM23SEL bits in
the Clock control register (SCU_CLKCNTR). When these pins are not used as clock inputs,
they can be configured as GPIO.
Clock control unit (CCU)
The CCU generates a master clock of frequency fMSTR. From this master clock the CCU
also generates individually scaled and gated clock sources to each of the following
functional blocks within the STR91xFA.
CPU, fCPUCLK
Advanced High Performance Bus (AHB), fHCLK
Advanced Peripheral Bus (APB) fPCLK
Flash memory interface (FMI), fFMICLK
UART Baud Rate Generators, fBAUD
USB, fUSB
Master clock sources
The master clock generated by the CCU (Clock Control Unit) has three clock sources that
you select using the MCLKSEL[1:0] bits in the Clock control register (SCU_CLKCNTR).
Under firmware control, the CPU can switch between the three CCU inputs without
introducing any glitches on the master clock output. The clock sources are the PLL output,
the oscillator input pin and the RTC clock:
The PLL takes the 4 to 25 MHz oscillator clock as input and generates a master clock
output up to 96 MHz. The fPLL output frequency is programmable. Typical frequencies
are 48 MHz, 66 MHz or 96 PLL MHz (maximum). By default, at power-up the master
clock is sourced from the main oscillator until the PLL is ready (locked) and then the
CPU may switch to the PLL source under firmware control. The CPU can switch back to
6/48
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AN2633 pdf, datenblatt
Power supply and clocks
AN2633
This allows you to dynamically control the number of peripherals that are running which
allows you to optimize the power used in a very flexible way.
The Idle mode gating mask register 0 (SCU_MGR0) and the Idle mode gating mask register
1 (SCU_MGR1) allow you to define a set of peripherals that are kept running when the
microcontroller goes into Idle mode. In Sleep mode, all peripherals except the RTC are
turned off.
Clock gating in emulation mode
During emulation mode (debug state of the ARM966E-S processor) the System Controller
allows gating the clock of a peripheral or a group of peripherals. The software application
can choose to stop the desired peripheral when ARM966E-S enters emulation mode. When
you clear the related bit in the Peripheral emulation clock gating register 0 (SCU_PECGR0),
or Peripheral emulation clock gating register 1 (SCU_PECGR1), the peripheral clock is
gated in emulation mode.
1.4
Note:
Power modes
The STR91xFA has configurable and flexible power management features that allow you to
choose the best power option to fit your application. You can dynamically manage the power
consumption or hardware to match the system's requirements. Power management is
provided via clock control to the CPU and individual peripherals. The STR91xFA supports
the following 4 global power control modes:
Normal Run mode
Special Interrupt Run mode
Idle mode
Sleep mode
In the application development environment, a special mode (Debug state) is active during
in circuit emulation (ICE). In this mode, the clocks are never switched off when the ICE is in
use even if the CPU enters Idle or Sleep mode. In Idle mode, the CPU stops fetching
instructions, but the ICE can override this state in order to run the debugger code. Using
Flash_PD_DBG bit in the Power management register (SCU_PWRMNG) you can configure
the Flash to enter power down mode when debug mode is active.
12/48
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