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F25L32QA-50PHG Schematic ( PDF Datasheet ) - ESMT

Teilenummer F25L32QA-50PHG
Beschreibung 3V Only 32 Mbit Serial Flash Memory
Hersteller ESMT
Logo ESMT Logo 




Gesamt 30 Seiten
F25L32QA-50PHG Datasheet, Funktion
ESMT
Flash
„ FEATURES
y Single supply voltage 2.7~3.6V
y Standard, Dual and Quad SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI;
200MHz / 344MHz / 400MHz equivalent Quad SPI)
y Low power consumption
- Active current: 35 mA
- Standby current: 30 μ A
- Deep Power Down current: 5 μ A
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
F25L32QA
3V Only 32 Mbit Serial Flash Memory
with Dual and Quad
y Erase
- Chip erase time 25 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
y Page Programming
- 256 byte per programmable page
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
Speed
Package
F25L32QA –50PAG
50MHz 8 lead SOIC 200mil
F25L32QA –86PAG
86MHz 8 lead SOIC 200mil
F25L32QA –100PAG 100MHz 8 lead SOIC 200mil
F25L32QA –50PHG
50MHz 16 lead SOIC 300mil
F25L32QA –86PHG
86MHz 16 lead SOIC 300mil
F25L32QA –100PHG 100MHz 16 lead SOIC 300mil
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
„ GENERAL DESCRIPTION
The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
E„lite Semiconductor Memory Technology Inc.
The device features sector erase architecture. The memory array
is divided into 1024 uniform sectors with 4K byte each; 64
uniform blocks with 64K byte each. Sectors can be erased
individually without affecting the data in other sectors. Blocks can
be erased individually without affecting the data in other blocks.
Whole chip erase capabilities provide the flexibility to revise the
data in the device. The device has Sector, Block or Chip Erase
but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Publication Date: Jan. 2010
Revision: 1.1
1/40
Free Datasheet http://www.Datasheet4U.com






F25L32QA-50PHG Datasheet, Funktion
ESMT
F25L32QA
Block
37
36
35
34
33
32
31
30
29
28
27
26
25
Table 1: F25L32QA Sector Address Table – Continued II
Sector
607
:
592
591
:
576
575
:
560
559
:
544
543
:
528
527
:
512
511
:
496
495
:
480
479
:
464
463
:
448
447
:
432
431
:
416
415
:
400
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
25F000H – 25FFFFH
:
250000H – 250FFFH
24F000H – 24FFFFH
:
240000H – 240FFFH
23F000H – 23FFFFH
:
230000H – 230FFFH
22F000H – 22FFFFH
:
220000H – 220FFFH
21F000H – 21FFFFH
:
210000H – 210FFFH
20F000H – 20FFFFH
:
200000H – 200FFFH
1FF000H – 1FFFFFH
:
1F0000H – 1F0FFFH
1EF000H – 1EFFFFH
:
1E0000H – 1E0FFFH
1DF000H – 1DFFFFH
:
1D0000H – 1D0FFFH
1CF000H – 1CFFFFH
:
1C0000H – 1C0FFFH
1BF000H – 1BFFFFH
:
1B0000H – 1B0FFFH
1AF000H – 1AFFFFH
:
1A0000H – 1A0FFFH
19F000H – 19FFFFH
:
190000H – 190FFFH
Block Address
A21 A20 A19 A18 A17 A16
100101
100100
100011
100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
6/40
Free Datasheet http://www.Datasheet4U.com

6 Page









F25L32QA-50PHG pdf, datenblatt
ESMT
F25L32QA
„ INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L32QA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
significant bit. CE must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instruction
Operation
Max.
Freq
1
SIN SOUT
Read
33 MHz 03H Hi-Z
Fast Read
Fast Read Dual Output12,13
Fast Read Dual I/O12, 14
0BH Hi-Z
3BH
BBH
Fast Read Quad
Output12, 15
Fast Read Quad I/O12, 16
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
6BH
EBH
20H Hi-Z
D8H Hi-Z
Chip Erase
60H /
C7H
Hi-Z
2
SIN SOUT
A23-A16 Hi-Z
A23-A16 Hi-Z
A23-A16
A23-A8
A23-A16
A23-A0, M7-M0
A23-A16 Hi-Z
A23-A16 Hi-Z
--
Bus Cycle 1~3
34
SIN SOUT
A15-A8 Hi-Z
A15-A8 Hi-Z
A15-A8
A7-A0, M7-M0
SIN SOUT
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0
DOUT0~1
A15-A8
A7-A0
X, DOUT0~1
A15-A8 Hi-Z
A15-A8 Hi-Z
DOUT2~6
A7-A0 Hi-Z
A7-A0 Hi-Z
- ---
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Quad Page Program17
Mode Bit Reset18
50MHz
32H
FFH Hi-Z
Deep Power Down (DP)
B9h Hi-Z
Read Status Register-1
(RDSR-1) 6
~ 05H Hi-Z
Read Status Register-2
(RDSR-2) 6
35H Hi-Z
Enable Write Status
Register (EWSR) 7
100MHz 50H Hi-Z
Write Status Register
(WRSR) 7
Write Enable (WREN) 10
01H Hi-Z
06H Hi-Z
Write Disable (WRDI)/ Exit
secured OTP mode
04H Hi-Z
Enter secured OTP mode
(ENSO)
B1H Hi-Z
Release from Deep Power
Down (RDP)
ABH Hi-Z
Read Electronic Signature
(RES) 8
ABH Hi-Z
RES in secured OTP mode
& not lock down
ABH Hi-Z
RES in secured OTP mode
& lock down
ABH Hi-Z
A23-A16
FFH
-
X
X
Hi-Z
-
DOUT
(S7-S0)
DOUT
(S15-S8)
--
A15-A8
--
--
--
--
--
DIN
(S7-S0)
-
Hi-Z
-
DIN
(S15-S8)
Hi-Z
--
- - --
- - --
- - --
X X XX
X X XX
X X XX
A7-A0
--
--
--
--
--
-. -
--
--
-. -
--
XX
XX
XX
5
SIN SOUT
X DOUT0
XX
X
cont.
6
SIN SOUT
X DOUT1
X DOUT0
DOUT0~1
-
N
SIN SOUT
X cont.
X cont.
cont.
-
X
cont.
--
--
DOUT0~3
-
--
--
cont.
-
--
--
------
DIN0 Hi-Z
DIN0~3
--
--
DIN1 Hi-Z
DIN4~7
--
--
Up to
256 Hi-Z
bytes
Up to 256
byte
--
--
------
------
------
------
------
------
------
------
X 15H - - - -
X 35H - - - -
X 75H - - - -
Table 5: Device Operation Instruction - Continued
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
12/40
Free Datasheet http://www.Datasheet4U.com

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