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C8051F588 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F588
Beschreibung Mixed Signal ISP Flash MCU Family
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F588 Datasheet, Funktion
Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Three Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 15 mA at 50 MHz;
Typical stop mode current: 230 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
Automotive Qualified
- Temperature Range: –40 to +125 °C
C8051F58x/F59x
Mixed Signal ISP Flash MCU Family
Memory
- 8448 bytes internal data RAM (256 + 8192 XRAM)
- 128 or 96 kB Banked Flash; In-system programma-
ble in 512-byte Sectors
- External 64 kB data memory interface programma-
ble for multiplexed or non-multiplexed mode
Digital Peripherals
- 40, 33, or 25 Port I/O; All 5 V push-pull with high
sink current
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Two Hardware enhanced UARTs, SMBus™, and
enhanced SPI™ serial ports
- Six general purpose 16-bit counter/timers
- Two 16-Bit programmable counter array (PCA)
peripherals with six capture/compare modules each
and enhanced PWM functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation.
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 48-Pin QFP/QFN (C8051F580/1/4/5)
- 40-Pin QFN (C8051F588/9-F590/1)
- 32-Pin QFP/QFN (C8051F582/3/6/7)
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-2 VREF
DIGITAL I/O
UART 0-1
SMBus
SPI
PCA x 2
Timers 0-5
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
128 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
8 kB XRAM
POR WDT
Rev. 1.2 4/11
Copyright © 2011 by Silicon Laboratories C8051F580/1/2/3/4/5/6/7/8/9-F590/1
Free Datasheet http://www.Datasheet4U.com






C8051F588 Datasheet, Funktion
C8051F58x/F59x
21.4. LIN Slave Mode Operation ............................................................................ 217
21.5. Sleep Mode and Wake-Up ............................................................................ 218
21.6. Error Detection and Handling ........................................................................ 218
21.7. LIN Registers................................................................................................. 219
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 219
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 221
22. Controller Area Network (CAN0) ........................................................................ 229
22.1. Bosch CAN Controller Operation................................................................... 230
22.1.1. CAN Controller Timing .......................................................................... 230
22.1.2. CAN Register Access............................................................................ 231
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 231
22.2. CAN Registers............................................................................................... 233
22.2.1. CAN Controller Protocol Registers........................................................ 233
22.2.2. Message Object Interface Registers ..................................................... 233
22.2.3. Message Handler Registers.................................................................. 233
22.2.4. CAN Register Assignment .................................................................... 234
23. SMBus................................................................................................................... 237
23.1. Supporting Documents .................................................................................. 238
23.2. SMBus Configuration..................................................................................... 238
23.3. SMBus Operation .......................................................................................... 238
23.3.1. Transmitter Vs. Receiver....................................................................... 239
23.3.2. Arbitration.............................................................................................. 239
23.3.3. Clock Low Extension............................................................................. 239
23.3.4. SCL Low Timeout.................................................................................. 239
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 240
23.4. Using the SMBus........................................................................................... 240
23.4.1. SMBus Configuration Register.............................................................. 240
23.4.2. SMB0CN Control Register .................................................................... 244
23.4.3. Data Register ........................................................................................ 247
23.5. SMBus Transfer Modes................................................................................. 247
23.5.1. Write Sequence (Master) ...................................................................... 248
23.5.2. Read Sequence (Master) ...................................................................... 249
23.5.3. Write Sequence (Slave) ........................................................................ 250
23.5.4. Read Sequence (Slave) ........................................................................ 251
23.6. SMBus Status Decoding................................................................................ 251
24. UART0 ................................................................................................................... 254
24.1. Baud Rate Generator .................................................................................... 254
24.2. Data Format................................................................................................... 256
24.3. Configuration and Operation ......................................................................... 257
24.3.1. Data Transmission ................................................................................ 257
24.3.2. Data Reception ..................................................................................... 257
24.3.3. Multiprocessor Communications ........................................................... 258
25. UART1 ................................................................................................................... 263
25.1. Enhanced Baud Rate Generation.................................................................. 264
25.2. Operational Modes ........................................................................................ 265
6 Rev. 1.2
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C8051F588 pdf, datenblatt
C8051F58x/F59x
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 23
Table 3.1. Pin Definitions for the C8051F58x/F59x ................................................. 24
Table 4.1. QFP-48 Package Dimensions ................................................................ 32
Table 4.2. QFP-48 Landing Diagram Dimensions ................................................... 33
Table 4.3. QFN-48 Package Dimensions ................................................................ 34
Table 4.4. QFN-48 Landing Diagram Dimensions ................................................... 35
Table 4.5. QFN-40 Package Dimensions ................................................................ 36
Table 4.6. QFN-40 Landing Diagram Dimensions ................................................... 37
Table 4.7. QFP-32 Package Dimensions ................................................................ 38
Table 4.8. QFP-32 Landing Diagram Dimensions ................................................... 39
Table 4.9. QFN-32 Package Dimensions ................................................................ 40
Table 4.10. QFN-32 Landing Diagram Dimensions ................................................. 41
Table 5.1. Absolute Maximum Ratings .................................................................... 42
Table 5.2. Global Electrical Characteristics ............................................................. 43
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 47
Table 5.4. Reset Electrical Characteristics .............................................................. 48
Table 5.5. Flash Electrical Characteristics .............................................................. 48
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 49
Table 5.7. Clock Multiplier Electrical Specifications ................................................ 50
Table 5.8. Voltage Regulator Electrical Characteristics .......................................... 50
Table 5.9. ADC0 Electrical Characteristics .............................................................. 51
Table 5.10. Temperature Sensor Electrical Characteristics .................................... 52
Table 5.11. Voltage Reference Electrical Characteristics ....................................... 52
Table 5.12. Comparator 0, 1 and 2 Electrical Characteristics ................................. 53
Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled) ........................... 94
Table 13.1. Special Function Register (SFR) Memory Map for
Pages 0x00, 0x10, and 0x0F .............................................................. 117
Table 13.2. Special Function Register (SFR) Memory Map for Page 0x0C .......... 119
Table 13.3. Special Function Registers ................................................................. 120
Table 14.1. Interrupt Summary .............................................................................. 128
Table 15.1. Flash Security Summary .................................................................... 141
Table 18.1. EMIF Pinout (C8051F580/1/4/5) ......................................................... 158
Table 18.2. EMIF Pinout (C8051F588/9-F590/1) .................................................. 159
Table 18.3. AC Parameters for External Memory Interface ................................... 173
Table 20.1. Port I/O Assignment for Analog Functions ......................................... 189
Table 20.2. Port I/O Assignment for Digital Functions ........................................... 189
Table 20.3. Port I/O Assignment for External Digital Event Capture Functions .... 190
Table 21.1. Baud Rate Calculation Variable Ranges ............................................ 213
Table 21.2. Manual Baud Rate Parameters Examples ......................................... 215
Table 21.3. Autobaud Parameters Examples ........................................................ 216
Table 21.4. LIN Registers* (Indirectly Addressable) .............................................. 221
Table 22.1. Background System Information ........................................................ 231
Table 22.2. Standard CAN Registers and Reset Values ....................................... 234
12 Rev. 1.2
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