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ST72321Rx Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer ST72321Rx
Beschreibung 64/44-pin 8-bit MCU
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
ST72321Rx Datasheet, Funktion
ST72321Rx
ST72321ARx ST72321Jx
64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC,
five timers, SPI, SCI, I2C interface
Features
Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C
Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliar voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator and bypass for
external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin on 64-pin devices
– 15/9 external interrupt lines (on 4 vectors)
Up to 48 I/O Ports
– 48/32/24 multifunctional bidirectional I/O lines
– 34/22/17 alternate function lines
– 16/12/10 high sink outputs
5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
LQFP64
14 x 14
LQFP32
7x7
LQFP64
10 x 10
LQFP44
10 x 10
– 8-bit PWM Auto-reload timer with: 2 input cap-
tures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector
3 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– I2C multimaster interface
1 Analog peripheral
– 10-bit ADC with up to 16 input ports
Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Table 1. Device summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range
Package
ST72321R9/ST72321AR9/ ST72321R7/ST72321AR7/
ST72321J9
ST72321J7
ST72321R6/ST72321AR6
Flash/ROM 60K
Flash/ROM 48K
Flash/ROM 32K
2048 (256)
1536 (256)
1024 (256)
3.8 to 5.5V
-40 to +125°C, -40 to +85°C
LQFP64 14x14 (R), LQFP64 10x10 (AR), LQFP44 10x10 (J)
March 2009
Rev 2
1/193
1
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ST72321Rx Datasheet, Funktion
Table of Contents
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 177
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.2 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.3 Reset pin protection with LVD Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.5 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.1.6 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 187
15.1.7 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1.8 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1.9 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.1.10 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.2 ALL FLASH DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.2.1 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.3 LIMITATIONS SPECIFIC TO REV Q AND REV S FLASH DEVICES . . . . . . . . . . . . . . . 189
15.3.1 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.4 LIMITATIONS SPECIFIC TO ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.4.1 LVD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.4.2 LVD Startup behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.3 AVD not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.4 Internal RC oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.5 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.6 Pull-up not present on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.7 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15.4.8 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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ST72321Rx pdf, datenblatt
ST72321Rx ST72321ARx ST72321Jx
Pin n°
Pin Name
Level
Port
Input
Output
Main
function
(after
reset)
Alternate function
45 - - PA2
46 31 16 PA3 (HS)
47 32 - VDD_1
48 33 - VSS_1
49 34 17 PA4 (HS)
50 35 - PA5 (HS)
51 36 18 PA6 (HS)/SDAI
52 37 19 PA7 (HS)/SCLI
I/O CT
I/O CT
S
HS
X
X
ei0
ei0
S
I/O CT HS X X
I/O CT HS X X
I/O CT HS X
I/O CT HS X
53 38 20 VPP/ ICCSEL
I
54 39 21 RESET
55 - - EVD
56 - - TLI
57 40 22 VSS_2
58 41 23 OSC23)
59 42 24 OSC13)
60 43 25 VDD_2
61 44 26 PE0/TDO
62 1 27 PE1/RDI
I/O CT
I CT
S
I/O
I
S
I/O CT
I/O CT
PE2 (Flash device)
X
XX
XX
X
63 -
-
PE2 (ROM device)
I/O CT
X
64 - - PE3
I/O CT
XX
X X Port A2
X X Port A3
Digital Main Supply Voltage
Digital Ground Voltage
X X Port A4
X X Port A5
T Port A6 I2C Data 1)
T Port A7 I2C Clock 1)
Must be tied low. In flash program-
ming mode, this pin acts as the pro-
gramming voltage input VPP. See
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices
Top priority non maskable interrupt.
External voltage detector
Top level interrupt input pin
Digital Ground Voltage
Resonator oscillator inverter output
External clock input or Resonator os-
cillator inverter input
Digital Main Supply Voltage
X X Port E0 SCI Transmit Data Out
X X Port E1 SCI Receive Data In
Port E2
Caution: In Flash devices this port is
always input with weak pull-up.
Port E2
Caution: In ROM devices, no weak
pull-up present on this port.
X X In LQFP44 this pin is not connected to
an internal pull-up like other unbond-
ed pins (See note 4). It is recommend-
ed to configure it as output push pull
to avoid added current consumption.
X X Port E3
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 46. and Section 12.8 I/O PORT PIN CHARACTER-
12/193
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